HY27SA161G1M Hynix Semiconductor, HY27SA161G1M Datasheet - Page 15
HY27SA161G1M
Manufacturer Part Number
HY27SA161G1M
Description
1gbit 128mx8bit / 64mx16bit Nand Flash Memory
Manufacturer
Hynix Semiconductor
Datasheet
1.HY27SA161G1M.pdf
(43 pages)
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Note: 1. If t
A9-A26(1)
A9-A26(1)
Note: 1. Highest address depends on device density.
Rev 0.5 / Oct. 2004
CE
RE
RB
CLE
ALE
WE
I/O
A0-A7
A0-A7
ELWL
Command
01h/ 50h
Code
00h/
is less than 10ns, t
(1st half Page)
(1st half Page)
Read A Command, x8 Devices
Area A
Area A
Read B Command, x8 Devices
Address Input
WLWH
(2nd half
(2nd half
Area B
Area B
Page)
Page)
must be minimum 35ns, otherwise, t
Figure 10. Read (A, B, C) Operation
Figure 11. Read Block Diagrams
tBLBH1
(read)
(Spare)
(Spare)
Area C
Area C
1Gbit (128Mx8bit / 64Mx16bit) NAND Flash
Busy
A9-A26(1)
A0-A2 (x16)
A9-A26(1)
A0-A3 (x8)
WLWH
Data Output (sequentially)
A0-A7
HY27UA(08/16)1G1M Series
HY27SA(08/16)1G1M Series
may be minimum 25ns.
Read A Command, x16 Devices
Area A
Read C Command, x8/x16 Devices
A4-A7 (x8), A3-A7 (x16) are don't care
(main area)
Area A
Area A/B
Area C
(Spare)
(50h)
Area C
15
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