ATA6020N ATMEL Corporation, ATA6020N Datasheet - Page 45

• Manufacturer Part Number: ATA6020N
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

5.2.7.5
4708D–4BMCU–09/05
9-bit Shift Mode
Figure 5-25. Example of 8-bit Synchronous Transmit Operation
Figure 5-26. Example of 8-bit Synchronous Receive Operation
In the 9-bit shift mode, the SSI is able to handle the MCL protocol (described below). It always
operates as an MCL master device, i.e., SC is always generated and output by the SSI. Both the
MCL start and stop conditions are automatically generated whenever the SSI is activated or
deactivated by the SIR-bit. In accordance with the MCL protocol, the output data is always
changed in the clock low phase and shifted in on the high phase.
Before activating the SSI (SIR = 0) and commencing an MCL dialog, the appropriate data direc-
tion for the first word must be set using the SDD control bit. The state of this bit controls the
direction of the data port (BP43 or MCL_SD). Once started, the 8 data bits are, depending on
the selected direction, either clocked into or out of the shift register. During the 9th clock period,
the port direction is automatically switched over so that the corresponding acknowledge bit can
be shifted out or read in. In transmit mode, the acknowledge bit received from the device is cap-
tured in the SSI Status Register (TACK) where it can be read by the controller. A receive mode,
the state of the acknowledge bit to be returned to the device is predetermined by the SSI Status
Register (RACK).
(IFN = 0)
(IFN = 1)
Interrupt
Interrupt
(IFN = 0)
(IFN = 1)
SRDY
Interrupt
Interrupt
ACT
SRDY
SIR
SD
SC
ACT
SIR
SD
SC
msb
7 6 5
Write STB
(tx data 1)
rx data 1
msb
4 3 2 1 0
7 6 5 4 3 2 1
tx data 1
lsb
msb
7 6 5
lsb
0
rx data 2
4 3 2 1 0
Write STB
(tx data 2)
lsb
msb
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
Write STB
(tx data 3)
tx data 2
Read SRB
(rx data 1)
lsb msb
msb
7 6 5 4 3 2 1 0
Read SRB
(rx data 2)
rx data 3
tx data 3
lsb
ATA6020N
lsb
Read SRB
(rx data 3)
0
7 6 5 4
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