ATA6020N ATMEL Corporation, ATA6020N Datasheet - Page 31

• Manufacturer Part Number: ATA6020N
• Description: Low-current Microcontroller For Watchdog Function
• Manufacturer: ATMEL Corporation

5.2.6
4708D–4BMCU–09/05
Timer 2
8-/12 Bit Timer for:
Timer 2 can be used as an interval timer for interrupt generation, as signal generator or as baud
rate generator and modulator for the serial interface. It consists of a 4-bit and an 8-bit up counter
stage which both have compare registers. The 4-bit counter stages of Timer 2 are cascadable
as a 12-bit timer or as an 8-bit timer with a 4-bit prescaler. The timer can also be configured as
an 8-bit timer and a separate 4-bit prescaler.
The Timer 2 input can be supplied via the system clock, the external input clock (T2I), the Timer
1 output clock or the shift clock of the serial interface. The external input clock T2I is not syn-
chronized with SYSCL. Therefore, it is possible to use Timer 2 with a higher clock speed than
SYSCL. Furthermore; with that input clock Timer 2 operates in the power-down mode SLEEP
(CPU core -> sleep and OSC-Stop -> yes) as well as in the POWER-DOWN (CPU core -> sleep
and OSC-Stop -> no). All other clock sources supplied no clock signal in SLEEP. The 4-bit
counter stages of Timer 2 have an additional clock output (POUT).
Its output has a modulator stage that allows the generation of pulses as well as the generation
and modulation of carrier frequencies. Timer 2 output can modulate with the shift register inter-
nal data output to generate Bi-phase- or Manchester-code.
If the serial interface is used to modulate a bit-stream, the 4-bit stage of Timer 2 has a special
task. The shift register can only handle bit-stream lengths divisible by 8. For other lengths, the
4-bit counter stage can be used to stop the modulator after the right bit-count is shifted out.
If the timer is used for carrier frequency modulation, the 4-bit stage works together with an addi-
tional 2-bit duty cycle generator like a 6-bit prescaler to generate carrier frequency and duty
cycle. The 8-bit counter is used to enable and disable the modulator output for a programmable
count of pulses.
The timer has a 4-bit and an 8-bit compare register for programming the time interval, t. For pro-
gramming the timer function, it has four mode and control registers. The comparator output of
stage 2 is controlled by a special compare mode register (T2CM). This register contains mask
bits for the actions (counter reset, output toggle, timer interrupt) which can be triggered by a
compare match event or the counter overflow. This architecture enables the timer function for
various modes.
Timer 2 compare data values.
Timer 2 has a 4-bit compare register (T2CO1) and an 8-bit compare register (T2CO2). Both
these compare registers are cascadable as a 12-bit compare register, or 8-bit compare register
and 4-bit compare register.
For 12-bit compare data value: m = x +1
For 8-bit compare data value: n = y +1
For 4-bit compare data value: I = z +1
• Interrupt, square-wave, pulse and duty cycle generation
• Baud rate generation for the internal shift register
• Manchester and Bi-phase modulation together with the SSI
• Carrier frequency generation and modulation together with the SSI
0 x 4095
0 y 255
0
z 15
ATA6020N
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