PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 412

• Manufacturer Part Number: PM5380-BI
• Description: Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
14.2 Receive ATM UTOPIA Level 3 System Interface
14.3 Transmit Packet over SONET/SDH (POS) Level 3 System
RADR[2:0]
The Receive UTOPIA Level 3 System Interface Timing diagram (Figure 41) illustrates the
operation of the system side receive interface. Assertion of the receive cell available output,
RCA, indicates that there is at least one ATM cell structure in the channel FIFO. Internally a
channel’s RCA status must only deassert one clock cycle after RSOC has been sampled high by
the layer device. A channel’s RCA may reassert at any time when a cell is received.
PHY selection occurs by setting the RADR[2:0] bus with the PHY address when RENB
changes from a high to a low value. RENB should deassert when the cell structure of the last
cell in the FIFO has finished being transferred. Once the cell transfer has started, the interface
cannot be paused. In the example, a 52-byte ATM cell structure read from a PHY. The PHY
channels are polled and PHY #0, #1 and #3 report they have at least one ATM cell. A cell is
then read from PHY #1.
RSOC is high during the first word of the ATM cell structure and is present for the start of each
cell. Thus, RSOC will mark the H1 to H4 bytes in the ATM cell structure. The length of the
cell structure can be configured for 52 and 56 bytes using the CELLFORM register in RUL3.
Figure 41 Receive UTOPIA Level 3 System Interface Timing
DAT[31:0]
Interface
The Packet over SONET/SDH (POS) Level 3 System Interface is compatible with the POS-
PHY Level 3 specification (see References). The S/UNI-8x155 only supports the 32-bit mode
of operation.
The Transmit POS Level 3 System Interface Timing diagram (Figure 42) illustrates the
operation of the system side transmit FIFO interface. Assertion of the transmit packet available
output, PTPA/STPA, indicates that the FIFO fill level is below the low water mark configured
by LWM[5:0]. De-assertion of the transmit packet available output occurs when the FIFO fill
level is above the high water mark configured by HWM[5:0]. When a channel is polled with
PTPA high and the upstream is ready to write data, the upstream device should select the PHY
using TSX and then assert TENB to write data. At any time, if the upstream does not have a
byte to write, it must de-assert TENB.
RPRTY
RFCLK
RSOC
RENB
RCA
W4
0
W5
1
W6
0
2
W7
1
3
W8
2
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
W9
3
W10
W11
W12
1
W13
1
W1
1
Released
W2
412
1
W3
W4