PM5380-BI PMC-Sierra, Inc., PM5380-BI Datasheet - Page 404

• Manufacturer Part Number: PM5380-BI
• Description: Network Interface, SATURN User Network Interface (8x155) Telecom Standard Product
• Manufacturer: PMC-Sierra, Inc.

Proprietary and Confidential to PMC-Sierra, Inc., and for its customers’ internal use.
Document No.: PMC- 2010299, Issue 2
13.15 Power Supplies
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Please refer to the S/UNI-16x155 reference design (PMC-2000506) for further
recommendations
Due to ESD protection structures in the pads it is necessary to exercise caution when powering a
device up or down. ESD protection devices behave as diodes between power supply pins and
from I/O pins to power supply pins. Under extreme conditions it is possible to blow these ESD
protection devices or trigger latch up. The recommended power supply sequencing follows:
1. The VDD supply must be applied before or at the same time as QAVD and AVD supplies
2. VDDI supplies must be applied after VDD has been applied or must be current limited to
3. VDD/VDDI supplies must be applied before digital input pins are driven or the current per
4. AVD supplies must be applied before analog input pins are driven or the current per pin
5. The differential voltage between VDD and AVD must be less than 1.0 volts including peak
6. Power down the device in the reverse sequence. Use the above current limiting technique
In order to optimize jitter generated by the CSU and the jitter tolerance of the CRU, we
recommend the following power filter scheme shown in Figure 33. Sensitive analog power pins
require RC filter networks in order to meet SONET/SDH jitter specifications. Some
recommended notes follows:
1. Place each 0.1 µF capacitor as close to its associated power pin as possible.
2. The 0.1 µF capacitors are ceramic X7R or X5R.
Low-pass filtering networks are recommended for analog power supplies as close to the
package pin as possible. Separate decoupling is required to prevent the transmitter from
coupling noise into the receiver and to prevent power supply transients from coupling into
some internal reference circuitry. See the section on Power Supplies for more details.
The high speed serial streams (TXD[7:0]+/- and RXD[7:0]+/-) must be routed with 50 ohm
controlled impedance circuit board traces and must be terminated with a matched load.
Normal TTL-type design rules are not recommended and will reduce the performance of the
device. See the section on interfacing to ECL and PECL devices for more details.
(the voltage difference between any two pins must be less than 0.5 volts) or the QAVD and
AVD supplies must be current limited to the maximum latch-up current specification.
the maximum latch-up current specification.
pin limited to less than the maximum DC input current specification.
limited to less than the maximum DC input current specification.
to peak noise. The differential voltage between VDD and QAVD must be less than 0.5 volts
including peak to peak noise. Otherwise, digital noise on VDD will be coupled into the
sensitive analog circuitry.
for the analog power supplies. Small offsets in VDD / AVD / VDDI discharge times will
not damage the device.
S/UNI®-8x155 ASSP Telecom Standard Product Data Sheet
Released
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