PM5361-RI PMC-Sierra, Inc., PM5361-RI Datasheet - Page 71

• Manufacturer Part Number: PM5361-RI
• Description: SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR
• Manufacturer: PMC-Sierra, Inc.

DATA SHEET
PMC-920526
Register 3FH, 5FH, 7FH: TU #4 in TUG2 #1 to TUG2 #7, LOP Interrupt
This register is used to identify and acknowledge loss of pointer interrupts for the
tributaries TU #4 in TUG2 #1 TO TUG2 #7.
LOP1I-LOP7I:
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
The LOP1I to LOP7I bits identify the source of loss of pointer interrupts. In
TU3 mode, these bits are unused and will return a logic 0 when read. When
the corresponding TUG2 tributary group is configured for TU2 (VT6), VT3, or
TU12 (VT2) mode, the associated LOP x I bit is unused and will return a logic
0 when read. When operational, the LOP1I to LOP7I bits report and
acknowledge LOP interrupt of TU #4 in TUG2 #1 to TUG2 #7, respectively.
Interrupts are generated upon loss of pointer and upon re-acquisition. An
LOP x I bit is set high when a loss of pointer event on the associated tributary
occurs and are cleared immediately following a read of this register, which
also acknowledges and clears the interrupt. LOP x I remains valid when
interrupts are not enabled (LOPE set low) and may be polled to detect loss of
pointer events.
Type
R
R
R
R
R
R
R
ISSUE 8
Function
Unused
LOP7I
LOP6I
LOP5I
LOP4I
LOP3I
LOP2I
LOP1I
Default
X
0
0
0
0
0
0
0
TRIBUTARY UNIT PAYLOAD PROCESSOR
63
PM5361 TUPP