PM5361-RI PMC-Sierra, Inc., PM5361-RI Datasheet - Page 61

• Manufacturer Part Number: PM5361-RI
• Description: SONET/SDH TRIBUTARY UNIT PAYLOAD PROCESSOR
• Manufacturer: PMC-Sierra, Inc.

DATA SHEET
PMC-920526
Register 27H, 47H, 67H: TU3 or TU #1 in TUG2 #1 to TUG2 #7, LOP Interrupt
This register is used to identify and acknowledge loss of pointer interrupts for the
tributaries TU #1 in TUG2 #1 TO TUG2 #7. It is also used to identify and
acknowledge TU3 loss of pointer interrupts.
LOP1I:
LOP2I-LOP7I:
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
The LOP1I bit identifies the source of loss of pointer interrupts. In TU3 mode,
the LOP1I bit reports and acknowledges LOP interrupt of the TU3 pointer.
Out of TU3 mode, the LOP1I bit reports and acknowledges LOP interrupt of
TU #1 in TUG2 #1. Interrupts are generated upon loss of pointer and upon
re-acquisition. LOP1I is set high when the corresponding loss of pointer
event occurs and are cleared immediately following a read of this register,
which also acknowledges and clears the interrupt. LOP1I remains valid when
interrupts are not enabled (LOPE set low) and may be polled to detect loss of
pointer events.
The LOP2I to LOP7I bits identify the source of loss of pointer interrupts. In
TU3 mode, these bits are unused and will return a logic 0 when read. Out of
TU3 mode, the LOP2I to LOP7I bits report and acknowledge LOP interrupt of
TU #1 in TUG2 #2 to TUG2 #7, respectively. Interrupts are generated upon
loss of pointer and upon re-acquisition. An LOP x I bit is set high when a loss
of pointer event on the associated tributary (TU #1 in TUG2 # x ) occurs and
are cleared immediately following a read of this register, which also
acknowledges and clears the interrupt. LOP x I remains valid when interrupts
Type
R/W
R
R
R
R
R
R
R
ISSUE 8
Function
ACCEL
LOP7I
LOP6I
LOP5I
LOP4I
LOP3I
LOP2I
LOP1I
Default
0
0
0
0
0
0
0
0
TRIBUTARY UNIT PAYLOAD PROCESSOR
53
PM5361 TUPP