STE2004SDIE2 STMicroelectronics, STE2004SDIE2 Datasheet - Page 69
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STE2004SDIE2
Manufacturer Part Number
STE2004SDIE2
Description
102 x 65 single-chip LCD controller/driver
Manufacturer
STMicroelectronics
Datasheet
1.STE2004SDIE2.pdf
(79 pages)
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STE2004S
Table 28. AC operation
1.
2. For bus line loads Cb between 100 and 400pF the timing parameters must be linearly interpolated
3. Trise and Tfall (30%-70%) -10ns
4.
5. All timing values are valid within the operating supply voltage and ambient temperature ranges and referenced to V
6. Cb is the capacitive load for each bus line.
Serial interface (
F
T
T
T
T
T
T
T
T
T
T
T
T
T
SCLK
CYC
PWH1
PWL1
S2
H2
PWH2
S3
H3
S4
H4
S5
H5
H6
Symbol
V
C
F
IH
VLCD
frame
with an input voltage swing of V
is the filtering capacitor on VLCD
=
Clock frequency
Clock cycle SCLK
SCLK pulse width HIGH
SCLK pulse width LOW
CS setup time
CS hold time
CS minimum high time
SD/C setup time
SD/C hold time
SDIN setup time
SDIN hold time
SDOUT access time
SDOUT disable time vs.
SCLK
SDOUT disable time vs.
CS
f
--------- -
960
osc
Figure 75
Parameter
)
SS
to V
V
V
V
V
DD
DD1
DD1
DD1
DD1
Test condition
= 1.7V;
= 1.7V
= 1.7V
= 1.7V
Min.
125
60
60
40
50
50
30
30
30
40
8
0
0
Typ.
Electrical characteristics
Max.
30
20
20
IL
and
MHz
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
69/79
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