MEA-224 Zarlink Semiconductor, Inc., MEA-224 Datasheet - Page 13

• Manufacturer Part Number: MEA-224
• Description: 4-Port, Layer 2 Fast Ethernet Access Controller
• Manufacturer: Zarlink Semiconductor, Inc.

XpressFlow-2001 Series –
Ethernet Switch Chip-set
4.2.5 Register Map
©
1997
Note: All 32-bit registers are D-word aligned.
Register Description
Device Configuration Registers (DCR)
Interrupt Controls
Buffer Memory Interface
FCB Buffer & Stack Management
GCR
DCR0
DCR1
DCR2
DCR3
DCR4
DTSR
ISR
ISRM
IMSK
IAR
MWAR
MRAR
MBAR
MWBS
MRBS
MWDR
MWDX
MRDR
MRDX
FCBBA
FCBAG Frame Control Buffer – Buffer Aging Status
FCBSL
FCBST
FCBSS
(57(; (7:25.6
All 16-bit registers are also D-word aligned and right justified.
This is a Global Register. CPU is allowed to write the Global Register of all devices by a sin-
These registers are reserved for system diagnostic usage only.
Global Control Register
Device Status Register
Signature & Revision Register
ID Register
Device Configuration Register
Interfaces Status Register
Test Register
Interrupt Status Register – Unmasked
Interrupt Status Register – Masked
Interrupt Mask Register
Interrupt Acknowledgment Register
Memory Write Address Reg. – Single Cycle
Memory Read Address Reg. – Single Cycle
Memory Address Register – Burst Mode
Memory Write Burst Size (in D-words)
Memory Read Burst Size (in D-words)
Memory Write Data Register
Memory Write Data Reg. – Byte Swapping
Memory Read Data Register
Memory Read Data Reg. – Byte Swapping
Frame Control Buffer – Base Address
Frame Ctrl Buffer Stack – Size Limit
Frame Ctrl Buffer Stack – Buffer Low Threshold
Frame Ctrl Buffer Stack – Allocation Status
For the Little Endian CPUs, register offset bit [1,0] are always set to be 00.
For the Big Endian CPUs, register offset bit [1,0] are always set to be 10.
gle operation.
P R E L I M I N A R Y
4-Port 10/100M Ethernet Access Controller
Page: 13
D A T A
Endian
hE6C
hE6C
hDA0
hFA0
hD00
hD30
hD90
hDB0
hF00
hF00
hF20
hF30
hF40
hF70
hF80
hF90
hFB0
hE08
hE18
hE28
hE40
hE50
hE68
hE68
hF10
Little
I/O Offset
S H E E T
Endian
hE6C
hE6C
hDA2
hDB2
hF32
hFA2
hFB2
hE18
hE52
hE68
hE68
hD02
hD32
hD92
hF02
hF02
hF12
hF22
hF42
hF72
hF82
hF92
hE08
hE28
hE42
Big
Rev. 4.0 –December, 1997
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
32-bit
32-bit
32-bit
32-bit
16-bit
16-bit
16-bit
16-bit
16-bit
16-bit
32-bit
32-bit
32-bit
16-bit
Size
Reg.
W/R
W/--
W/R
W/R
W/R
W/R
W/--
W/R
W/R
W/R
W/R
W/R
W/--
W/R
W/R
W/R
W/--
--/R
--/R
--/R
--/R
--/R
--/R
--/R
--/R
--/R
EA-224
Note:
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