MEA-224 Zarlink Semiconductor, Inc., MEA-224 Datasheet - Page 10

• Manufacturer Part Number: MEA-224
• Description: 4-Port, Layer 2 Fast Ethernet Access Controller
• Manufacturer: Zarlink Semiconductor, Inc.

XpressFlow-2001 Series –
Ethernet Switch Chip-set
4.2 Management Bus Interface
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4.2.1 Pin Description
©
1997
Supports various industry standard micro-
processors including:
Easily adapts to other industry standard CPUs
Provides separate Address and Data bus
Supports Big & Little Endian byte ordering
Intel 186, 386, and 486 family or equivalent
Motorola MPC series embedded processors
P_C[4:0]
P_A[11:1] TTL In (5VT) Address Bus Bit [11:1] – I/O port address
P_D[15:0] TTL I/O-TS
P_ADS#
P_RWC
P_RDY#
P_BS16# TTL Out-OD Bus Size 16 – response to bus master that the EA208 only supports 16-
P_CS#
P_INT
P_RST#
P_CLK
Symbol
(57(; (7:25.6
CMOS Input Processor Configuration bit [4:0] : – During the Reset Cycle, the
(5VT)
TTL In (5VT) Address Strobe – indicates valid address is on the bus
TTL Input
(5VT)
TTL Out-OD Data Ready – timing indicates for bus data valid
TTL Input
(5VT)
CMOS Out-
put
TTL In-ST
(5VT)
TTL In (5VT) CPU Clock – 2X Clock for 386 family, and 1X Clock for the others
P R E L I M I N A R Y
Type
Name & Functions
P_C[4:0] pins provides the processor configuration. By using external
weak pull-up or -down resistors, they define the External Management
Bus Interface Configuration. These inputs are sampled at the trailing
edge of the Reset cycle.
After RESET, these pins are used as XpressFlow Bus Data bit [31:27].
Data Bus Bit [15:0] – a 16-bit synchronous data bus.
Read/Write Control – indicates the current bus cycle is a read or write
cycle. C[1] defines the polarity of this signal during the Reset cycle.
bit data bus width.
Chip Select – indicates the XpressFlow Engine is the target for the cur-
rent bus operation.
Interrupt Request to Switch Manager CPU The polarity of this signal
output is programmable via chip configuration register .
CPU Reset – Synchronous reset Input from Switch Manager CPU
Lo
Hi
C[0] – Defines the CPU Clock input is 1X or 2X clock
C[1] – Selects either Big or Little Endian byte ordering
C[2] – Defines the polarity of the P_RWC (Rd/Wr Control) input
C[3] – Defines the CPU Bus width – For EA-208, it is default to 16-bit CPU
C[4] – Defines the timing relationship between P_RDY and P_D[15:0] valid.
C[1]=0
C[1]=1
CPU Clock
1X Clock
Bus interface, and the setting of this bit is ignored.
If C[4] is High, the P_D[15:0] are valid along in the same clock period
as P_RDY is asserted. If C[4] is Low, the P_RDY is asserted one
clock period early ahead of the P_D[15:0] are valid.
4-Port 10/100M Ethernet Access Controller
2x Clock
C[0]
P_R/W# is used for PowerPC or other similar processors.
P_W/R# is used for 386, 486 or other similar processors
Page: 10
Little Endian
Byte Order
Big Endian
D A T A
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C[1]
Supports 16-bit Data Bus
Supports early RDY cycle
Supports 1X or 2X CPU Clock
Provides a single interrupt signal to Switch
Manager CPU
Meets timing requirement for Intel/AMD
186 family processors
2X CPU Clock for 386 family processors
P_R/W#
P_W/R#
RWC
C[2]
S H E E T
Bus Size
Rev. 4.0 –December, 1997
C[3]
n/a
n/a
RDY Timing
Normal
Early
C[4]
EA-224