T8531TLDB Agere Systems, Inc., T8531TLDB Datasheet - Page 30

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T8531TLDB

Manufacturer Part Number
T8531TLDB
Description
CODEC, AMuLaw CODEC, Line Card Signal Processor for CODEC Chip Set, 64TQFP
Manufacturer
Agere Systems, Inc.
Datasheet
Codec Chip Set
Timing Characteristics
* Card address 0, bit offset 0 assumed.
† Card address 0 assumed.
Notes:
A is the position of the frame sync pulse in the delayed mode.
B is the position of the frame sync pulse in the nondelayed mode.
30
SDR
SDX
SCK
SFS
*
A
tSFHSCL
Figure 9. Timing Characteristics of PCM Interface Assuming 2.048 MHz SCK Rate
1
B
1
tSCLSFL
1
tSCHDXV
2
tFSHFSL
2
2
3
3
3
TIME SLOT 0
4
(continued)
4
4
tDRVSCL
5
5
tSCLDRX
5
6
6
6
7
7
7
8
8
8
9
10
11
TIME SLOT 1
12
13
tSCHSCL
tSCLSCH
14
Agere Systems Inc.
February 2002
15
16
5-4233 (F).a
1
1
1

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