T8531TLDB Agere Systems, Inc., T8531TLDB Datasheet - Page 29

• Manufacturer Part Number: T8531TLDB
• Description: CODEC, AMuLaw CODEC, Line Card Signal Processor for CODEC Chip Set, 64TQFP
• Manufacturer: Agere Systems, Inc.

February 2002
Agere Systems Inc.
Timing Characteristics
A signal is valid if it is above V
fication, the following conditions apply:
Table 16. PCM Interface Timing (See Figure 9.)
tSCH1SCH2 Rise Time of SCK
tSCL2SCL1 Fall Time of SCK
All input signals are defined as V
tR is measured from V
Delay times are measured from the input signal valid to the output signal valid.
Setup times are measured from the data input valid to the clock input invalid.
Hold times are measured from the clock signal valid to the data input invalid.
Pulse widths are measured from V
tSCHSCL
tSCLSCH
tSCHDXV
tSCLDRX
tSFHSCL
tDRVSCL
tFSHFSL
tSCLSFL
Symbol
fSCK
tSCK
—
Frequency of SCK (Selection
Period of SCK High
Period of SFS High
Frame Sync High Setup
Frame Sync Hold Time
Data Enabled on TS Entry
Period of SCK
Jitter of SCK
Period of SCK Low
Receive Data Setup
Receive Data Hold
frequency is pin-strap
programmable.)
Parameter
IL
to V
IH
IH
or below V
. tF is measured from V
IL
IL
= 0.4 V, V
to V
IL
IL
and invalid if it is between V
or from V
Measured from V
Measured from V
Measured from V
Measured from V
Measured from V
Measured from V
IH
0 < C
= 2.7 V, tR < 10 ns, tF < 10 ns.
Test Conditions
2.048 MHz
4.096 MHz
LOAD
IH
IH
to V
—
—
—
—
—
—
to V
< 100 pF
IH
IL
.
IH
IH
IL
IH
IL
IL
.
to V
to V
to V
to V
to V
to V
IH
IL
IL
IH
IL
IL
:
IL
0.488
0.244
Min
and V
80
80
30
30
30
30
—
—
—
—
—
—
0
IH
1/fSCK
. For the purposes of this speci-
2.048
4.096
Typ
—
—
—
—
—
—
—
—
—
—
—
9
100 ms = 1 ppm
Codec Chip Set
100 ns in
Max
62.5
62.5
15
15
90
—
—
—
—
—
—
—
—
—
Unit
MHz
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
—
29
s
s