T8531TLDB Agere Systems, Inc., T8531TLDB Datasheet - Page 13

• Manufacturer Part Number: T8531TLDB
• Description: CODEC, AMuLaw CODEC, Line Card Signal Processor for CODEC Chip Set, 64TQFP
• Manufacturer: Agere Systems, Inc.

February 2002
Chip Set Functional Description
(continued)
Receive Path
In the receive direction, the signal received from the system
interface is converted to a 16-bit linear PCM signal.
Receive Path Filtering
The 16-bit linear PCM signal is filtered and interpolated to
16 ksamples/s to meet the receive signal loss characteristics.
This filter smooths the data following interpolation from
8 ksamples/s to 16 ksamples/s. The filter can also serve as an
equalizer for frequency response alteration. This is required for
complex termination impedance cases when using a current
feed, voltage-sensed SLIC.
One of two receive filters can be used, the receive filter and
the extended receive filter. The receive filter has two poles and
three zeros. This filter can be used to minimize downloadable
code (to use this receive filter, select the T7531x codec in the
Aquarium coefficient software). The extended receive filter
provides more flexibility in coefficient optimization by providing
three poles and three zeros. The Aquarium coefficient soft-
ware defaults to the extended receive filter when the T8531x
codec is selected.
Digital Receive Gain
The receive absolute and relative gains are specified as 15-bit
binary numbers representing their linear magnitude. These
gains default to 4000 Hex. This equates to a 0 dB gain for the
relative gain but equates to a –0.211 dB gain for the absolute
gain. For a 0 dB gain, program the absolute gain for 4193 Hex.
Gain can be varied from minus infinity dB (0) (0000 Hex) to
6 dB for relative gain or to 5.8 dB for absolute gain (7FFF Hex).
The relative gain control allows for TLP adjustment without
hybrid balance or termination coefficient modification.
Interpolator and Digital Sigma-Delta Modulator
The sampling frequency of the receive signal from the digital
gain adjustment is increased from 16 kHz to 64 kHz by the
interpolator, which removes most of the high-frequency signal
images above 8 kHz. The interpolator also maps each of 16
time slots to the appropriate line channel through the digital
sigma-delta modulator.
The digital sigma-delta modulator converts the interpolated
signal to a 1.024 MHz bit stream which is then sent to the
T8532 device.
Decoder, Filters, and Receive Amplifier
Receive data enters the T8532 on pins OSDR[1:0] at
4.096 MHz; four channels are time-division multiplexed onto
each pin. The data is demultiplexed into eight individual chan-
nels. The processed signal for each channel passes through
Agere Systems Inc.
switched-capacitor D/A and reconstruct filters, followed by a
smoothing filter. A programmable gain amplifier is included,
followed by an output amplifier capable of driving a 50 k
load to 1.58 V single-ended (relative to
ferential at peak overload. For single-ended operation, the
load must be ac coupled to VRP (or VRN).
Other Chip Set Functions
Voltage Reference
The T8532 has a precision on-chip voltage reference which
ensures accurate and highly stable transmission levels.
Hybrid Balance
The hybrid balance function is provided as a digital block in
the T8531.
The T8531 implements a 9-tap FIR and a single-pole IIR digi-
tal balance filter in which a replica of the echo is digitally sub-
tracted from the transmit plus near-end echo signal. The
coefficients are user programmable on a per-line basis via the
microprocessor interface.
Analog Termination Impedance Synthesis
Termination impedance matching is implemented to maximize
the power transfer capability at the loop interface and to mini-
mize signal reflections between the transmit and receive
paths.
The resistive component, implemented in the T8532 device,
comprises a variable attenuated path between VTX and VRP.
The capacitive component is implemented in the digital
domain.
Analog termination impedance (ATI) is provided with 16 gain
settings to match a voltage drive/current sense line interface
circuit with the following characteristics:
Z
where Z
resistance of each protection resistor (for stability R
G
and A
is positive (positive voltage swing on VTX gives a positive
voltage swing on VRP). The gain values are shown in Table
26; gain tolerances are 2%. Differential receive output is
assumed.
Digital Termination Impedance Synthesis
The CTZ filter in the T8531 synthesizes complex termination
impedances. The CTZ filter utilizes alpha and beta coeffi-
cients (board control words 4 and 5, respectively) to perform
the synthesis. One set of alpha beta coefficients is required
for each termination impedance and balance network.
T
TX
= 2R
is the SLIC transmit gain, G
T
is the T8532 feedback gain. The polarity of the A
P
T
+ G
is the termination impedance in ohms, R
TX
* G
RX
* A
T
RX
is the SLIC receive gain,
Codec Chip Set
VOS
) or 3.16 V dif-
P
P
is the
50 ),
T
gain
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