T8531TLDB Agere Systems, Inc., T8531TLDB Datasheet - Page 12

• Manufacturer Part Number: T8531TLDB
• Description: CODEC, AMuLaw CODEC, Line Card Signal Processor for CODEC Chip Set, 64TQFP
• Manufacturer: Agere Systems, Inc.

Codec Chip Set
Chip Set Functional Description
Transmit Path
Antialias Filter and - Converter
The line interface circuit must provide a transmit signal,
VTX, and a reference voltage, VRTX, which is the dc
voltage of the VTX signal for that channel.
The input signal goes into a programmable-gain ampli-
fier. The signal is then passed through an antialias filter
followed by a - A/D converter. The - converter
operates at 1.024 MHz. The processed output signals
are multiplexed into two groups of four channels each
onto output pins OSDX[1:0], each of which operates at
4.096 MHz.
A precision, on-chip voltage reference helps ensure
accurate and highly stable transmission levels.
It is important to understand the difference between
how the gain levels should be set in the T8532 and how
these levels would be set in a standard codec. The
T8532 is best thought of as a data acquisition system,
not a codec. Hybrid balance, fine gain adjust, -law or
A-law coding, filtering, and equalization are done after
the A/D in the T8532 and by the DSP processor in the
T8531. The analog gain adjust taps should not be used
to set the absolute level at the PCM output. This can be
done using the DSP gain adjust taps. The analog taps
should be set so the signal at the input to the A/D con-
verter is as close as possible to the full-scale input level
of the A/D for the largest signal level that will be present
at the VTX input. This optimizes the dynamic range of
the A/D. The 0 dB gain tap should thus be used if the
maximum signal level is in the range between
2.25 Vp-p and 3.2 Vp-p. The 3 dB tap should be used
for signals with a maximum signal level in the range of
1.6 Vp-p and 2.25 Vp-p. The 6 dB tap should be used
for signals with a maximum signal level in the range
between 1.1 Vp-p and 1.6 Vp-p. Higher gain levels
should be used for signals with smaller absolute levels.
The signal level to produce a 0 dBm0 level at the digital
transmit output of the T8531 is not a fixed quantity as
explained above. For a line with a complex impedance
or an RX echo signal, extra headroom must be allowed
and the TX signal level must be set to account for the
headroom. In this specification, the largest possible
0 dBm0 level for the TX signal is assumed. This guar-
antees that the distortion specification will not be
exceeded for all practical 0 dBm signal levels. The larg-
est possible 0 dBm signal is one that has no headroom
for TX gain equalization. For the case of 0 dB transmit
gain, this level is found as:
(3.2 V/log
12
12
–1
(3.15/20)) = 2.23 Vp-p.
This level is the worst-case 0 dBm0 level.
Decimator
The decimator filters out the high-frequency compo-
nents and down-samples to 16 kHz. It also reorders the
16 channels of transmit signals into a sequence that is
determined by the time-slot assignment.
Digital Transmit Gain Adjustment
The transmit absolute and relative gains are specified
as 15-bit binary numbers representing their linear mag-
nitude. These gains default to 4000 Hex. This equates
to a 0 dB gain for the relative gain but equates to a
1.65 dB gain for the absolute gain. For a 0 dB gain, pro-
gram the absolute gain for 34ED Hex. Gain can be var-
ied from minus infinity dB (off) (0000 Hex) to 6 dB for
relative gain or to 7.65 dB for absolute gain (7FFF
Hex).
The relative gain control allows for TLP adjustment
without hybrid balance or termination coefficient modifi-
cation.
Band Filtering
The bandpass filter in the transmit path removes power
line and ringing frequencies, and eliminates most of the
signal energy at 4 kHz and above. This allows the
encoder to transmit the filtered signal at 8 ksamples/s,
the worldwide standard.
The transmit filtering is implemented with a low-pass fil-
ter, followed by a high-pass filter. The data samples
enter the filter at 16 ksamples/s. They are first low-pass
filtered to 3.4 kHz. After low-pass filtering, the sampling
rate is reduced to 8 ksamples/s. The samples are then
high-pass filtered to 300 Hz.
The low-pass filter also serves as an equalizer for fre-
quency response alterations. A set of equalizer coeffi-
cients that modify this filter are required for each
complex termination impedance when using a voltage
feed, current-sensed SLIC.
In the transmit path, the 8 ksamples/s PCM signal out-
put from the filter is processed prior to transmission
over the system interface. The 16-bit linear PCM signal
may be compressed according to either -law or A-law,
or transmitted as two consecutive 8-bit words. The
selection is programmable via the microprocessor
interface. Please note, when using A-law, a linear value
of 0 is always encoded as 7F.
-Law, A-Law, and Linear PCM Modes
Agere Systems Inc.
February 2002