MSAN-107 Zarlink Semiconductor, Inc., MSAN-107 Datasheet - Page 4

• Manufacturer Part Number: MSAN-107
• Description: Understanding and Eliminating Latch-Up in CMOS Applications
• Manufacturer: Zarlink Semiconductor, Inc.

drain diffusions are two emitters of the transistor:
one tied to V
substrate acts as the base and hence, is in common
with the collector of the vertical NPN. The P- well is
the collector of the PNP which is also base of the
NPN. Due to the shared diffusions, the vertical NPN
and lateral PNP transistors are effectively connected
as an SCR (Fig. 5). This parasitic SCR is connected
directly across the supply rails.
triggered, it can cause excessive current to flow. The
SCR is normally turned off for nominal operating
supply voltages and with all output voltages within
the power supply limits. This SCR may be externally
triggered causing the output structure to latch-up.
The triggering mechanism can be any one of those
mentioned in the previous section.
Output voltages being forced outside of the power
supply limits is the most common cause of output
latch-up. Two parameters are defined at this point
for use in subsequent discussions. These are I
and V
the output structure to cause latch-up to occur. V
is the voltage excursion outside of the power supply
rails at the output pin that results in I
through the output structure. In other words I
V
result in latch-up triggering. These same parameters
also apply to input latch-up (see next section).
Consider first an output voltage which goes below
V
output base-emitter junction of the vertical NPN
transistor to become forward biased. Since this acts
as the SCR gate, triggering occurs. Current is pulled
from V
the P- well, causing a localized drop across this
diffusion.
base-emitter junction of the NPN which is referenced
to V
and a low impedance path is created from V
V
A-34
LU
SS
SS
.
SS
by more than V
are the conditions at the output pin that will
LU
. Once this occurs, latch-up will be sustained
DD
. I
through the lateral PNP and is injected into
LU
This voltage drop will forward bias the
DD
is the current which must flow through
and the other to the output. The N-
LU
. This causes the P- well to
Hence, when
Figure 5 - Output SCR Structures
LU
flowing
LU
DD
and
LU
LU
to
A note must be taken here in regard to the amount of
over-voltage required to trigger latch-up.
above paragraph, it was mentioned that voltages
exceeding the supply rails by more than V
cause a current I
latch-up. The guaranteed values quoted in the data
sheet are 0.3V and 10mA respectively for these
parameters.
testing and hence, appear in the Absolute Maximum
Ratings for Zarlink devices. In practice, it is more
likely to require from 0.6V to 2V of over-voltage and
from 50 to several hundred milliamps of current to
cause output latch-up to occur. For input latch-up to
occur, it can take several volts of over-voltage and
similar currents to induce latch-up due to the series
resistance of the input protection circuitry (Fig. 6)
When the V
greater than V
this case, the output to substrate base-emitter
junction of the lateral PNP becomes forward biased.
Collector current from this transistors injected into
the P- well, again causing a lateral voltage drop.
This voltage drop causes the P- well to V
referenced base-emitter junction of the NPN to
become forward biased. This transistor’s collector
current, pulled from the substrate, causes a lateral
voltage drop across the substrate. This voltage drop,
in turn, will forward bias the V
base-emitter junction of the PNP. Thus, latch-up will
be sustained even if the output over-voltage
condition is removed and a low impedance path
again exists between V
There are two other causes of output latch-up that
are less likely to occur, but nonetheless must be
noted. The first of these is the result of over-voltages
on the power supply pins.
between V
maximum
breakdown of the reverse biased substrate to P- well
collector base junction of the bipolar transistors.
DD
DD
rating)
and V
These limits are used in production
LU
supply rail is exceeded by a voltage
, a similar set of events occurs. In
SS
LU
can
(i.e., greater than the absolute
DD
to flow and hence trigger
and V
cause
Application Note
SS
Excessive voltage
.
DD
an
to substrate
avalanche
LU
In the
.
will
SS