MSAN-107 Zarlink Semiconductor, Inc., MSAN-107 Datasheet
MSAN-107
Related parts for MSAN-107
MSAN-107 Summary of contents
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... By implementing the suggested techniques and circuitry, the designer can gain the advantages of CMOS circuitry without major concern about latch-up related problems. ANODE Figure 1 - Four-Layer SCR Structure MSAN-107 ISSUE 1 July 1993 Basically of parasitic, four-layer bipolar technology. By developing N 1 GATE P 2 ...
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... MSAN-107 Semiconductor Device Considerations Background on SCR’s Prior to discussing latch-up in CMOS devices advantageous to briefly review the basic theory of SCR operation. This will be helpful in developing an understanding of the relationships between external circuit and system conditions and the resultant triggerng of latch-up in CMOS devices. The basic SCR structure is that of a four-layer device as shown in Fig ...
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... One emitter is tied to V the output. A wide base lateral PNP transistor is formed when a P-channel device is located close to a N-channel transistor. The P-channel source and INPUT It is Each of Figure 4 - Typical Output Circuit MSAN-107 and The SCR is formed as The N- and the other to ...
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V and the other to the output. The N- DD substrate acts as the base and hence common with the collector of the vertical NPN. The P- ...
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... PNP transistor. When the input voltage goes negative, the gate of the SCR is turned on as mentioned. However, this second collector now referenced injects current into the P- well causing a second SCR DD MSAN-107 referenced diode SS and V , and DD SS For this latch- ...
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Figure 8 - Input SCR Structure with V Latch-Up Inducing Forced I/O Conditions Condition V (Volts) LU Outputs above V 1.9 DD Outputs below V 1.0 SS Inputs above V 1.9 DD Inputs below V 25.0 SS Table 1. MD74SC540AC ...
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... In this situation, C connected in series. The +12 volts applied to C causes the voltage at the ground point to increase in If driven Figure 10 - Local Decoupling Scheme in MSAN-107 CIRCUIT PCB containing such Assume that all is much 1 ...
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... MSAN-107 accordance with the charge sharing between This voltage could approach 12 volts since 2 » When the ground 1 2 connection, the voltage at the nominal 5V rail will jump up by the amount of voltage initially present at the ground point (i.e. almost 12V). This results in an over-voltage condition being applied to the devices supplied by the 5V rail ...
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... In this case there is the added concern when three-state outputs are tied together. over-voltage triggering of latch-up. present a high impedance only to signals lying within the power supply voltages. It must be stressed that MSAN-107 CMOS Device V ...
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... MSAN-107 these over-voltage conditions need only exist for a very brief period of time to trigger latch-up. Thus, even transient over-voltages during power-up may pose a problem. To ensure proper power supply sequencing, careful attention must be paid to the selection of decoupling components both at the initial design stage and when design revisions are done ...
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... At Figure 16 - Effects of Switching DC Loads Combined with Large Bus Capacitors MSAN-107 the same time, the bus capacitance tends to hold the voltage on the inputs and outputs connected to the bus at the full supply voltage sufficient voltage ...
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... MSAN-107 Minimizing intertrack capacitance by interleaving signal and ground tracks should be done wherever board space permits. Alternatively, clamping diodes can be connected on tracks exhibiting these voltage excursions. The diodes may need be Schottky diodes if regular ones do not clamp soon enough toprevent current flow through ...
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... Fig not feasible. The output resistance in this case needs to be substantially lower Digital and Analog Devices in Same System I n systems which have digital and analog devices powered by different supply voltages, there is the MSAN-107 . A-43 ...
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... MSAN-107 Fig Voltage Divider to Limit Voltage Swing on CMOS Input potential hazard of over-voltage developing. Consider, for example, the case of an analog comparator powered from digital device powered from a +10V supply. When the comparator output goes low, it will approach -10V and pull the digital input below V comparator can pull enough current, then latch-up may be triggered ...
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