MSAN-107 Zarlink Semiconductor, Inc., MSAN-107 Datasheet - Page 11

• Manufacturer Part Number: MSAN-107
• Description: Understanding and Eliminating Latch-Up in CMOS Applications
• Manufacturer: Zarlink Semiconductor, Inc.

Application Note
solution exists. All outputs should be kept in a high
impedance state during power-up and power-down.
Thus, no current will be available to trigger latch-up
even if differential supply voltages develop from
board to board.
resistors can be connected in series with any inputs
or outputs that may be subjected to over-voltages.
These resistors are sized to limit current to less than
10mA:
where V
The side effects of connecting these resistors are the
same as mentioned previously for power supply
over-voltage protection. There will be reductions in
current drive from outputs, in speed, and in noise
immunity on outputs driving DC loads through these
resistors
Devices Driving Long Address or Data Buses
Long address and data buses can exhibit quite large
capacitances. Devices which drive such buses or
have their inputs tied to one, can be subjected to
over-voltage conditions.
large DC current loads are switched on the same
PCB (e.g. a group of LED’s during a lamp test).
Over-voltages can develop as follows. The change
in the power supply current causes a localized
voltage drop on the supply pins of the devices near
to the device drawing the load current. This is a
result of the finite resistance of the power supply
tracks and contact resistance of any connectors. At
voltage differential between power supplies
.
Diff
R =
= maximum instantaneous
Figure 16 - Effects of Switching DC Loads Combined with Large Bus Capacitors
(V
Alternatively, current limiting
Diff
10mA
- 0.3V)
This is especially true if
the same time, the bus capacitance tends to hold the
voltage on the inputs and outputs connected to the
bus at the full supply voltage. If a sufficient voltage
differential develops between the bus and the local
power supply, then the bus capacitance will
discharge via the input and output structures. This
current can attain a magnitude of tens of milliamps
and hence trigger latch-up (Fig. 16).
Various precautions can be taken to reduce the
chances of this problem occurring.
power supply resistance and bus capacitances can
be done at the time of inital design. Wide power
supply tracks and low contact resistance connectors
should be used whenever possible. Buses should be
kept as short as possible and have the largest
possible spacings between the lines. If this problem
still results due to system restraints on PCB layout,
then the connection of a decoupling capacitor across
the power supply pins of the devices latching-up
should help (Fig. 17).
depends upon the magnitude of the local current and
the local resistance of the power supply. Normally a
10 F capacitor will clear up such problems and
should not interfere with the local power supply
sequencing on most PCB’s.
There is one other way in which an input/output
over-voltage can occur on long buses. There exists,
on such buses, intertrack capacitance as well as
capacitance to ground. When two adjacent tracks
are at opposite logic levels (one at 5V, the other at
ground), this capacitance charges to the full supply
voltage. When the track initially at ground potential
suddenly goes high, the signal is coupled through
the capacitor to the other track. The voltage on this
track increases from its initial value of 5V, impressing
over-voltages on any devices connected to this track.
The size of the capacitor
MSAN-107
Reducing the
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