HFA3861AIN Intersil Corporation, HFA3861AIN Datasheet - Page 8

• Manufacturer Part Number: HFA3861AIN
• Description: Processor, Direct Sequence Spread Spectrum Base band Processor
• Manufacturer: Intersil Corporation

Test Port
The HFA3861A provides the capability to access a number of
internal signals and/or data through the Test port, pins TEST
7:0. The test port is programmable through configuration
register (CR 34). Any signal on the test port can also be read
Power Down Modes
The power consumption modes of the HFA3861A are
controlled by the following control signals.
Receiver Power Enable (RX_PE, pin 61), which disables the
receiver when inactive.
Transmitter Power Enable (TX_PE, pin 62), which disables
the transmitter when inactive.
Reset (RESET, pin 63), which puts the receiver in a sleep
mode. The power down mode where, both RESET and
RX_PE are used is the lowest possible power consumption
mode for the receiver. Exiting this mode requires a
maximum of 10µs before the device is operational.
The contents of the Configuration Registers are not effected
by any of the power down modes. No reconfiguration is
required when returning to operational modes. Activation of
RESET does corrupt learned values of AGC settings and
noise floor values. Optimum receiver operation may not be
achieved until these values are reestablished (typically
<50µs of operation in noise only needed). The power
savings of activating RESET must be weighed against this.
Table 2 describes the power down modes available for the
HFA3861A (V
other inputs to the part (MCLK, SCLK, etc.) continue to run
except as noted.
SLEEP
MODE
CC
Inactive
RX_PE
= 3.3V). The table values assume that all
Inactive
TX_PE
8
HFA3683
RESET
Active
44MHz
1mA
HFA3783
TABLE 2. POWER DOWN MODES
AT
FIGURE 6. AGC CIRCUIT
Both transmit and receive functions disabled. Device in sleep mode. Control
Interface is still active. Register values are maintained. Device will return to its active
state within 10µs.
HFA3861A
RX_RF_AGC
RX_IF_DET
RX_IF_AGC
RX_Q±
RX_I±
from configuration register (CR50) via the serial control port.
Additionally, the transmit DACs can be configured to show
signals in the receiver via CR 14. This allows visibility to
analog like signals that would normally be very difficult to
capture.
Transmitter Description
The HFA3861A transmitter is designed as a Direct
Sequence Spread Spectrum Phase Shift Keying (DSSS
PSK) modulator. It can handle data rates of up to 11Mbps
(refer to AC and DC specifications). The various modes of
the modulator are Differential Binary Phase Shift Keying
(DBPSK) for 1Mbps, Differential Quaternary Phase Shift
Keying (DQPSK) for 2Mbps, and Complementary Code
Keying (CCK) for 5.5Mbps and 11Mbps. These implement
data rates as shown in Table 3. The major functional blocks
of the transmitter include a network processor interface,
DPSK modulator, high rate modulator, a data scrambler and
a spreader, as shown in Figure 7. CCK is essentially a
quadra-phase form of M-ARY Orthogonal Keying. A
description of that modulation can be found in Chapter 5 of:
“Telecommunications System Engineering”, by Lindsey and
Simon, Prentis Hall publishing.
The preamble is always transmitted as the DBPSK
waveform while the header can be configured to be either
DBPSK, or DQPSK, and data packets can be configured
for DBPSK, DQPSK, or CCK. The preamble is used by the
receiver to achieve initial PN synchronization while the
header includes the necessary data fields of the
communications protocol to establish the physical layer
link. The transmitter generates the synchronization
preamble and header and knows when to make the DBPSK
to DQPSK or CCK switchover, as required.
THRESH.
DETECT
HFA3861A
Q ADC
I ADC
DAC
IF
1
1
7
6
6
DEVICE STATE
DEMOD
AGC
CTL
I/O
DATA I/O