HFA3861AIN Intersil Corporation, HFA3861AIN Datasheet - Page 14

• Manufacturer Part Number: HFA3861AIN
• Description: Processor, Direct Sequence Spread Spectrum Base band Processor
• Manufacturer: Intersil Corporation

each antenna. An initial value of the noise floor is
established within 50µs of the chip being active and is
refined as goes on. Deasserting RX_PE does not corrupt the
learned values. If the absolute power metric is chosen, this
threshold is normally set to between -70 and -80dBm.
If desired, ED may be used in the acquisition process as well
as CCA. ED may be used to mask (squelch) weak signals
and prevent radio reception of signals too weak to support
the high data rates, signals from adjacent cells, networks, or
buildings. See CR48.
The Configuration registers effecting the CCA algorithm
operation are summarized below (more programming details
on these registers can be found under the Control Registers
section of this document).
The CCA output from pin 60 of the device can be defined as
active high or active low through CR 1 (bit 2).
CR9(6:5) allow CCA to be programmed to be a function of
ED only, the logical operation of (CS1 OR SQ1), the logical
function of (ED AND (CS1 OR SQ1)), or (ED OR (CS1 OR
SQ1)).
CR11(3) lets the user select from sampled CCA mode,
which means CCA will not glitch, is updated once per symbol
and is valid for reading at 15.8µs or 19.8µs. In non-sampled
mode, CCA may change at anytime, potentially several
times per slot, as ED and CS1 operate asynchronously to
slot times.
In a typical system CCA will be monitored to determine when
the channel is clear. Once the channel is detected busy,
CCA should be checked periodically to determine if the
channel becomes clear. CCA can be programmed to be
stable to allow asynchronous sampling or even falling edge
detection of CCA. Once MD_RDY goes active, CCA is then
ignored for the remainder of the message. Failure to monitor
CCA until MD_RDY goes active (or use of a time-out circuit)
could result in a stalled system as it is possible for the
channel to be busy and then become clear without an
MD_RDY occurring.
AGC Description
The AGC system consists of the 3 chips handling the receive
signal, the RF to IF downconverter, the IF to baseband
converter, and the baseband processor. The AGC loop is
digitally controlled by the BBP. Basically it operates as
follows:
Initially, the radio is set for high gain. The percent of time that
the A/D converters in the baseband processor are saturated
is monitored along with signal amplitude and the gain is
adjusted down until the amplitude is what will optimize the
demodulator’s performance. If the amount of saturation is
great, the initial gain adjust steps are large. If the signal
overload is small, they are less. If the signal level then varies
more than a preset amount, the AGC is declared unlocked
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HFA3861A
and the gain again allowed to readjust. When the gain is
right and the A/Ds’ outputs are within the lock window, the
BBP declares AGC lock and stops adjusting for the duration
of the packet.
We look for this locked state following an unlocked state as
one indication that a received signal is on the antenna. This
starts the receive process of looking for PN correlation.
Once PN correlation and AGC lock are found, the processor
begins acquisition.
For large signals, the power level in the RF stage output is
also monitored and if it is large, the LNA stage is shut down.
This removes 30dB of gain from the receive chain which is
compensated for by replacing 30dB of gain in the IF AGC
stage. There is some hysteresis in this operation. This
improves the receiver dynamic range.
Demodulator Description
The receiver portion of the baseband processor, performs A/D
conversion and demodulation of the spread spectrum signal.
It correlates the PN spread symbols, then demodulates the
DBPSK, DQPSK, or CCK symbols. The demodulator
includes a frequency tracking loop that tracks and removes
the carrier frequency offset. In addition it tracks the symbol
timing, and differentially decodes (where appropriate) and
descrambles the data. The data is output through the RX
Port to the external processor.
The PRISM baseband processor, HFA3861A uses
differential demodulation for the initial acquisition portion of
the message processing and then switches to coherent
demodulation for the MPDU demodulation. The HFA3861A
is designed to achieve rapid settling of the carrier tracking
loop during acquisition. Rapid phase fluctuations are
handled with a relatively wide loop bandwidth which is then
stepped down as the packet progresses. Coherent
processing improves the BER performance margin as
opposed to differentially coherent processing for the CCK
data rates.
The baseband processor uses time invariant correlation to
strip the PN spreading and phase processing to demodulate
the resulting signals in the header and DBPSK/DQPSK
demodulation modes. These operations are illustrated in
Figure 13 which is an overall block diagram of the receiver
processor.
In processing the DBPSK header, input samples from the I
and Q A/D converters are correlated to remove the
spreading sequence. The peak position of the correlation
pulse is used to determine the symbol timing. The sample
stream is decimated to the symbol rate and corrected for
frequency offset prior to PSK demodulation. Phase errors
from the demodulator are fed to the NCO through a lead/lag
filter to maintain phase lock. The carrier is de-rotated by the
carrier tracking loop. The demodulated data is differentially