HFA3861AIN Intersil Corporation, HFA3861AIN Datasheet - Page 13

• Manufacturer Part Number: HFA3861AIN
• Description: Processor, Direct Sequence Spread Spectrum Base band Processor
• Manufacturer: Intersil Corporation

At 11Mbps, 8 bits (d0 to d7; d0 first in time) are transmitted
per symbol.
The first dibit (d0, d1) encodes ϕ1 based on DQPSK. The
DQPSK encoder is specified in Table 6 above. The phase
change for ϕ1 is relative to the phase ϕ1 of the preceding
symbol. In the case of rate change, the phase change for ϕ1
is relative to the phase ϕ1 of the preceding CCK symbol. All
odd numbered symbols of the MPDU are given an extra 180
degree (π) rotation in accordance with the DQPSK
modulation as shown in Table 7. Symbol numbering starts
with “0” for the first symbol of the MPDU.
The data dibits: (d2, d3), (d4, d5), (d6, d7) encode ϕ2, ϕ3,
and ϕ4 respectively based on QPSK as specified in Table 7.
Note that this table is binary, not Grey, coded.
TX Power Control
The transmitter power can be controlled by the MAC via two
registers. The first register, CR58, contains the results of
power measurements digitized by the HFA3861A. By
comparing this measurement to what the MAC needs for
transmit power, the MAC can determine whether to raise or
lower the transmit power. It does this by writing the power
level desired to register CR31.
DIBIT PATTERN (d(0), d(1))
d2, d3
d(0) IS FIRST IN TIME
DIBIT PATTERN (d(i), d(i+1))
00 :
01 :
10 :
11 :
d(i) IS FIRST IN TIME
TABLE 6. 5.5Mbps CCK ENCODING TABLE
-1j
-1j
1j
1j
00
01
11
10
TABLE 5. DQPSK ENCODING TABLE
TABLE 7. QPSK ENCODING TABLE
00
01
10
11
-1
-1
1
1
-1j
-1j
1j
1j
EVEN SYMBOLS
PHASE CHANGE
13
3
-1
-1
π
1
1
(+j
/2 (-
π
0
π
/2
ω)
π
-1j
-1j
/2)
1j
1j
3
π
PHASE
1
1
1
1
PHASE CHANGE
ODD SYMBOLS
/2 (-
π
π
0
/2
3
π
π
(+j
/2 (-
/2)
-1j
-1j
1j
1j
π
π
0
/2
ω
π
)
/2)
1
1
1
1
HFA3861A
Clear Channel Assessment (CCA) and
Energy Detect (ED) Description
The clear channel assessment (CCA) circuit implements the
carrier sense portion of a carrier sense multiple access (CSMA)
networking scheme. The Clear Channel Assessment (CCA)
monitors the environment to determine when it is feasible to
transmit. The CCA circuit in the HFA3861A can be
programmed to be a function of RSSI (energy detected on the
channel), CS1, SQ1, or both. The CCA output can be ignored,
allowing transmissions independent of any channel conditions.
The CCA in combination with the visibility of the various internal
parameters (i.e., Energy Detection measurement results), can
assist an external processor in executing algorithms that can
adapt to the environment. These algorithms can increase
network throughput by minimizing collisions and reducing
transmissions liable to errors.
There are three measures that can be used in the CCA
assessment. The receive signal strength indication (RSSI)
which indicates the energy at the antenna, CS1 and carrier
sense (SQ1). SQ1 becomes active only when a spread
signal with the proper PN code has been detected, and the
peak correlation amplitude to sidelobe ratio exceeds a set
threshold, so it may not be adequate in itself.
CS1 becomes active anytime the AGC portion of the circuit
becomes unlocked, which is likely at the onset of a signal
that is strong enough to support 11Mbps, but may not occur
with the onset of a signal that is only strong enough to
support 1 or 2MBps. CS1 stays active until the AGC locks
and a SQ1 assessment is done, if SQ1 is false, then CS1 is
cleared, which deasserts CCA. If SQ1 is true, then tracking
is begun, and CCA continues to show the channel busy.
CS1 may occur at any time during acquisition as the AGC
state machine runs asynchronously with respect to slot
times.
A SQ1 evaluation occurs whenever the AGC has remained
locked for the entire data ingest period, when this happens,
SQ1 is updated between 8 and 9µs into the 10µs dwell. If
CS1 is not active, two consecutive SQ1’s are required to
advance the part to tracking.
The state of CCA is not guaranteed from the time RX_PE
goes high until the first CCA assessment is made. At the end
of a packet, after RXPE has been deasserted, the state of
CCA is also not guaranteed.
The receive signal strength indication (RSSI) measurement
is derived from the state of the AGC circuit. ED is the
comparison result of RSSI against a threshold. The
threshold may be set to an absolute power value, or it may
be set to be N dB above the measured noise floor. See CR
38. The HFA3861A measures and stores the RSSI level
when it detects no presence of BPSK or QPSK signals. The
smallest value of a 256 value buffer is taken to be the noise
floor. Thus, the value of the noise floor will adapt to the
environment. A separate noise floor value is maintained for