11257-801 AMI Semiconductor, Inc., 11257-801 Datasheet - Page 8

• Manufacturer Part Number: 11257-801
• Description: Low-Skew Clock Fanout Buffer ICs
• Manufacturer: AMI Semiconductor, Inc.

4.2.6
sequential registers, starting by default at Register 0. The
Block Write command, as noted in Figure 11, begins with
the seven-bit SMBus device address followed by a logic-
low R/W bit to begin a Write command. Following an ac-
knowledge of the SMBus address and R/W bit by the
slave device, a command code is written. It is defined
that all eight bits of the command code must be zero (0).
After the command code of zero and an acknowledge,
the host then issues a byte count that describes the
number of data bytes to be written. According to SMBus
convention, the byte count should be a value between 0
and 32; however this slave device ignores the byte count
value.
Following an acknowledge of the byte count, data bytes
may be written starting with Register 0 and incrementing
sequentially. An acknowledge by the device between
each byte of data must occur before the next data byte is
sent.
4.2.7
The Block Read command, shown in Figure 12, permits
the master to read several bytes of data from sequential
Figure 11: Block Write (SMBus)
Figure 12: Block Read (SMBus)
SMBus
S
S
Device Address
Device Address
START
Command
START
Command
DEVICE ADDRESS
DEVICE ADDRESS
7-bit Receive
7-bit Receive
SMBus: Block Write
SMBus: Block Read
W
W
From bus host
to device
The Block Write command permits the
master to write several bytes of data to
From bus host
to device
A
A
WRITE Command
WRITE Command
Acknowledge
Acknowledge
Command Code
Command Code
A S
From device
to bus host
A
From device
to bus host
Acknowledge
Acknowledge
Device Address
Repeat START
BYTE COUNT = N
Byte Count
DEVICE ADDRESS
7-bit Receive
R
A
A
READ Command
Acknowledge
Acknowledge
DATA BYTE 1
BYTE COUNT = N
Byte Count
8
Data
registers, starting by default at Register 0. To perform a
Block Read procedure the R/W bit that is transmitted af-
ter the seven-bit SMBus address is a logic-low, as in the
Block Write procedure. The write bit resets the register
address pointer to zero. Following an acknowledge of the
SMBus address and R/W bit by the slave device, a com-
mand code is written. It is defined that all eight bits of the
command code must be zero (0).
Following an acknowledge by the slave, the master gen-
erates a repeated START condition. The repeated
START terminates the write procedure, but not until after
the slave’s address pointer is set. The slave SMBus ad-
dress is then resent, with the R/W bit set this time to a
logic-high, indicating to the slave that data will be read.
The slave will acknowledge the device address, and then
will expect a byte count value (which will be ignored).
Following the byte count value, the device will take com-
mand of the bus and will transmit all the data beginning
with Register 0. After the last byte of data, the master
does not acknowledge the transfer but does generate a
STOP condition.
If the master does not want to receive all the data, the
master can not acknowledge the last data byte and then
can issue a STOP condition of the next clock.
A
A
Acknowledge
Acknowledge
DATA BYTE 1
Acknowledge
Data
STOP Command
A
DATA BYTE N
Acknowledge
Data
NO Acknowledge
DATA BYTE N
STOP Command
A
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Data
January 1999
A
1.13.99
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