11257-801 AMI Semiconductor, Inc., 11257-801 Datasheet - Page 5

• Manufacturer Part Number: 11257-801
• Description: Low-Skew Clock Fanout Buffer ICs
• Manufacturer: AMI Semiconductor, Inc.

January 1999
4.0
This integrated circuit is a read/write slave device that
supports both the Inter IC Bus (I
Management Bus (SMBus) two-wire serial interface pro-
tocols. The unique device address that is written to the
device determines whether the part expects to receive
SMBus commands or I
derived from the I
is very similar.
In general, the bus has to be controlled by a master de-
vice that generates the serial clock SCL, controls bus
access, and generates the START and STOP conditions
while the device works as a slave. Both master and slave
can operate as a transmitter or receiver, but the master
device determines which mode is activated. A device that
sends data onto the bus is defined as the transmitter, and
a device receiving data as the receiver.
Bus logic levels and timing parameters noted herein fol-
low I
centage of VDD. A logic-one corresponds to a nominal
voltage of VDD, while a logic-zero corresponds to ground
(VSS).
4.1
Data transfer on the bus can only be initiated when the
bus is not busy. During the data transfer, the data line
(SDA) must remain stable whenever the clock line (SCL)
is high. Changes in the data line when the clock line is
high is interpreted by the device as a START or STOP
condition. Both I
following conditions on the bus. Refer to Figure 13: Bus
Timing Data for more information.
4.1.1
Both the data (SDA) and clock (SCL) lines remain high to
indicate the bus is not busy.
4.1.2
A high to low transition of the SDA line while the SCL in-
put is high indicates a START condition. All commands to
the device must be preceded by a START condition.
4.1.3
A low to high transition of the SDA line while SCL is held
high indicates a STOP condition. All commands to the
device must be followed by a STOP condition.
2
C-bus convention. Logic levels are based on a per-
Dual Serial Interface Control
Bus Conditions
Not Busy
START Data Transfer
STOP Data Transfer
2
C-bus and SMBus protocols define the
2
C-bus, the protocol for both bus types
2
C commands. Since SMBus is
2
C-bus) and the System
5
4.1.4
The state of the SDA line represents valid data if the SDA
line is stable for the duration of the high period of the SCL
line after a START condition occurs. The data on the
SDA line must be changed only during the low period of
the SCL signal. There is one clock pulse per data bit.
Each data transfer is initiated by a START condition and
terminated with a STOP condition. The number of data
bytes transferred between START and STOP conditions
is determined by the master device, and can continue
indefinitely. However, data that is overwritten to the de-
vice after the data registers are filled will overflow from
the last register into the first register, then the second,
and so on, in a first-in, first-overwritten fashion.
4.1.5
When addressed, the receiving device is required to gen-
erate an Acknowledge after each byte is received. The
master device must generate an extra clock pulse to co-
incide with the Acknowledge bit. The acknowledging de-
vice must pull the SDA line low during the high period of
the master acknowledge clock pulse. Setup and hold
times must be taken into account.
The master must signal an end of data to the slave by not
generating an acknowledge bit on the last byte that has
been read (clocked) out of the slave. In this case, the
slave must leave the SDA line high to allow the master to
generate a STOP condition.
4.2
All programmable registers can be accessed via the bi-
directional two wire digital interface. The device accepts
the Random Register Read/Write and the Sequential
Register Read/Write I
supports the Block Read/Write SMBus commands.
4.2.1
After generating a START condition, the bus master
broadcasts a seven-bit device address followed by a R/W
bit. Note that every device on an I
have a unique address to avoid bus conflicts.
For an SMBus interface, the address of the device is:
A6
1
Data Valid
Acknowledge
I
2
Bus Operation and Commands
C-bus and SMBus Device Addressing
A5
1
A4
0
2
C commands. The device also
A3
1
2
C-bus or SMBus must
A2
0
A1
0
A0
1
1.13.99