11257-801 AMI Semiconductor, Inc., 11257-801 Datasheet - Page 20

• Manufacturer Part Number: 11257-801
• Description: Low-Skew Clock Fanout Buffer ICs
• Manufacturer: AMI Semiconductor, Inc.

Series termination adds no dc loading to the driver, and
requires less power than other resistive termination
methods. Further, no extra impedance exists from the
signal line to a reference voltage, such as ground.
As shown in Figure 20, the sum of the driver’s output im-
pedance (z
must equal the line impedance (z
Note that when the source impedance (z
matched to the line impedance, then by voltage division
the incident wave amplitude is one-half of the full signal
amplitude.
The full signal amplitude may take up to twice as long as
the propagation delay of the line to develop, reducing
noise immunity during the half-amplitude period. Note
also that the voltage at the receive end must add up to a
signal amplitude that meets the receiver switching
thresholds. The slew rate of the signal is also reduced
due to the additional RC delay of the load capacitance
and the line impedance. Also note that the output driver
impedance will vary slightly with the output logic state
(high or low).
8.2
High-speed clock drivers require careful attention to
power dissipation. Transient power (P
be derived from
where C
voltage, f
number of switching outputs.
The internal heat (junction temperature, T
the power dissipation can be calculated from
where
ambient temperature, and P
8.3
Connection of devices to a standard-mode implementa-
tion of either the I
shown in Figure 21. Selection of the pull-up resistors (R
and the optional series resistors (R
SCL lines depends on the supply voltage, the bus ca-
Dynamic Power Dissipation
load
JA
Serial Communications
CLK
is the package thermal resistance, T
O
) and the series termination resistance (R
P
is the load capacitance, V
T
V
is the clock frequency, and N
i
V
2
T
C-bus or the SMBus is similar to that
V
DD
J
R
(
2
z
S
O
(
z
C
JA
O
load
z
T
R
L
is derived above.
S
R
P
)
T
S
z
L
f
). That is,
O
)
CLK
z
.
T
L
S
A
T
) on the SDA and
) consumption can
V
N
DD
2
J
SW
) generated by
is the supply
sw
O
+R
A
is the
is the
S
) is
S
P
)
)
20
pacitance, and the number of connected devices with
their associated input currents.
Control of the clock and data lines is done through open
drain/collector current-sink outputs, and thus requires
external pull-up resistors on both lines. A guideline is
where t
and C
device on each DIMM, an I
and two other bus devices results in values in the 5k
7k
against high voltage spikes on the bus will alter the val-
ues for R
Figure 21: Connections to the Serial Bus
8.3.1
More detailed information on serial bus design can be
obtained from SMBus and I
the Intel Corporation at http://www.intel.com.
Information on the I
The I
tions),
http://www-us2.semiconductors.philips.com.
Additional information on the System Management Bus
can be found in the System Management Bus Specifica-
tion,
Implementers’ Forum at http://www.sbs-forum.org.
Clock Out
TRANSMITTER
SDA
range. Use of a series resistor to provide protection
(optional)
2
SCL
bus
C-bus And How To Use It (Including Specifica-
available
r
For More Information
R
available
is the maximum rise time (minus some margin)
P
is the total bus capacitance. Assuming an I
S
.
Data In
R
Data Out
P
(optional)
from
2
from
C-bus can be found in the document
R
R
S
P
the
2
2
2
Philips
C controller, the clock buffer,
C Bus Design , available from
Clock In
RECEIVER
t
C
r
R
Smart
P
bus
(optional)
,
R
Semiconductors
S
Battery
Data In
Data Out
January 1999
(optional)
R
System
S
1.13.99
2
to
at
C