11257-801 AMI Semiconductor, Inc., 11257-801 Datasheet - Page 19

• Manufacturer Part Number: 11257-801
• Description: Low-Skew Clock Fanout Buffer ICs
• Manufacturer: AMI Semiconductor, Inc.

January 1999
8.0
8.1
The primary concern when designing the board layout for
this device is the reduction of electromagnetic interfer-
ence (EMI) generated by the 18 copies of the 100MHz
SDRAM clock. It is assumed the reader is familiar with
basic transmission line theory.
8.1.1
To obtain the best performance, noise should be mini-
mized on the power and ground supplies to the IC. Ob-
serve good high-speed board design practices, such as:
Use multi-layer circuit boards with dedicated low im-
pedance power and ground planes for the device
(denoted as CLK VDD and CLK GND in Figure 19).
The device power and ground planes should be
completely isolated from the motherboard power and
ground planes by a void in the power planes.
Several low-pass filters using low impedance ferrite
ple the device power and ground planes from the
motherboard power and ground planes (MB VDD and
MB GND). The beads should span the gap between
the power and ground planes. Seven beads for
power and seven beads for ground are suggested
(14 total) so that the clock rise times (1V/ns) can be
maintained.
Place 1000pF bypass capacitors as close as possible
to the power pins of the IC. Use RF-quality low-
inductance multi-layer ceramic chip capacitors. Six
capacitors is optimal, one on each power/ground
grouping as shown in Figure 19.
Load similar clock outputs equally, and keep output
loading as light as possible to help reduce clock skew
and power dissipation.
Use equal-length clock traces that are as short as
possible. Rounded trace corners help reduce reflec-
tions and ringing in the clock signal.
The clock traces must never cross the void area be-
tween power/ground planes. Each trace must have a
complete plane (either VDD or GND) under the com-
plete length of the trace.
Application Information
Reduction of EMI
Layout Guidelines
u-
19
Figure 19: Board Layout
8.1.2
A signal reflection will occur at any point on a PC-board
trace where impedance mismatches exist. Reflections
cause several undesirable effects in high-speed applica-
tions, such as an increase in clock jitter and a rise in
electromagnetic emissions from the board. Using a prop-
erly designed series termination on each high-speed line
can alleviate these problems by eliminating signal reflec-
tions.
Figure 20: Series Termination
Component
Layer
Output Driver Termination
MB VDD
VOID
DRIVER
1000pF
1000pF
1000pF
MB GND
R
R
R
R
R
R
R
R
R
MB VDD
S
S
S
S
S
S
S
S
S
CLK VDD
z
1
2
4
5
8
9
11
13
14
17
18
21
24
O
Signal Layer
CLK GND
CLK VDD
R
S
LINE
z
CLK GND
L
48
47
45
44
41
40
38
36
35
32
31
28
25
MB GND
MB VDD
RECEIVE
MB GND
1000pF
1000pF
1000pF
R
R
R
R
R
R
R
R
R
S
S
S
S
S
S
S
S
S
1.13.99