74HC125D,653 NXP Semiconductors, 74HC125D,653 Datasheet - Page 10

• Manufacturer Part Number: 74HC125D,653
• Description: IC BUFFER DVR TRI-ST QD 14SOICN
• Manufacturer: NXP Semiconductors
• Series: 74HCr

Specifications of 74HC125D,653

• Logic Type: Buffer/Line Driver, Non-Inverting
• Package / Case: 14-SOIC (3.9mm Width), 14-SOL
• Number Of Elements: 4
• Number Of Bits Per Element: 1
• Current - Output High, Low: 7.8mA, 7.8mA
• Voltage - Supply: 2 V ~ 6 V
• Mounting Type: Surface Mount
• Logic Family: 74HC
• Number Of Channels Per Chip: 4
• Polarity: Non-Inverting
• Supply Voltage (max): 6 V
• Supply Voltage (min): 2 V
• Maximum Operating Temperature: 125 C
• Mounting Style: SMD/SMT
• High Level Output Current: - 7.8 mA
• Input Bias Current (max): 8 uA
• Low Level Output Current: 7.8 mA
• Maximum Power Dissipation: 500 mW
• Minimum Operating Temperature: - 40 C
• Number Of Lines (input / Output): 8 / 4
• Output Type: 3-State
• Propagation Delay Time: 9 ns
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 568-1392-2; 74HC125D-T; 933756990653

Philips Semiconductors
HC TYPES
AC waveforms 74HC
AC waveforms 74HC
March 1988
handbook, full pagewidth
HCMOS family characteristics
(1) In Fig.4 the active transition of the clock is going from LOW-to-HIGH and the active level of the forcing signals (SET, RESET
(2) For AC measurements: t
Fig.4
and PRESET) is HIGH. The actual direction of the transition of the clock input and the actual active levels of the forcing signals
are specified in the individual device data sheet.
Fig.3 Input rise and fall times, transition times and propagation delays for combinatorial logic ICs.
Set-up times, hold times, removal times, propagation delays and the maximum clock pulse frequency for
sequential logic ICs.
OUTPUT
PRESET
CLOCK
RESET,
INPUT
INPUT
INPUT
r
DATA
SET,
= t
f
= 6 ns; when measuring f
handbook, halfpage
INPUT
OUTPUT
10 %
50%
t su
t rem
50%
t r
10%
50%
t PLH
90%
t PHL
t THL
t WH
10%
max
90%
50%
90%
t h
, there is no constraint on t
t r
1/f max
t TLH
50%
90%
t f
50%
10%
10
t WL
t su
t f
t PHL
t PLH
t TLH
r
, t
f
with 50% duty factor.
MGK564
t h
FAMILY SPECIFICATIONS
t THL
V CC
GND
MGK569
V CC
GND
V CC
GND
V CC
GND