IDT74FCT163244CPAG IDT, Integrated Device Technology Inc, IDT74FCT163244CPAG Datasheet - Page 4
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IDT74FCT163244CPAG
Manufacturer Part Number
IDT74FCT163244CPAG
Description
IC BUFF DVR 16BIT N-INV 48TSSOP
Manufacturer
IDT, Integrated Device Technology Inc
Series
74FCTr
Datasheet
1.IDT74FCT163244CPAG.pdf
(6 pages)
Specifications of IDT74FCT163244CPAG
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
4
Number Of Bits Per Element
4
Current - Output High, Low
8mA, 24mA
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
48-TSSOP
Logic Family
FCT
Logical Function
Buffer/Line Driver
Number Of Elements
4
Number Of Channels
16
Number Of Inputs
16
Number Of Outputs
16
Operating Supply Voltage (typ)
3.3V
Output Type
3-State
Polarity
Non-Inverting
Propagation Delay Time
5.8ns
High Level Output Current
-8mA
Low Level Output Current
24mA
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
2.7V
Quiescent Current
10uA
Technology
CMOS
Pin Count
48
Mounting
Surface Mount
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
74FCT163244CPAG
800-1596
800-1596-5
800-1596
800-1596
800-1596-5
800-1596
SWITCHING CHARACTERISTICS OVER OPERATING RANGE
NOTES:
1. For conditions shown as Min. or Max., use appropriate value specified under Electrical Characteristics for the applicable device type.
2. Typical values are at V
3. Per TTL driven input. All other inputs at V
4. This parameter is not directly testable, but is derived for use in Total Power Supply Calculations.
5. Values for these conditions are examples of the I
6. I
NOTES:
1. Propagation Delays and Enable/Disable times are with V
2. See test circuit and waveforms.
3. Minimum limits are guaranteed but not tested on Propagation Delays.
4. Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.
POWER SUPPLY CHARACTERISTICS
IDT74FCT163244A/C
3.3V CMOS 16-BIT BUFFER/LINE DRIVER
Symbol
t
t
t
t
t
t
t
PLH
PHL
PZH
PZL
PHZ
PLZ
SK(o)
Symbol
I
I
ΔI
D
N
I
f
N
fi = Input Frequency
Ni = Number of Inputs at fi
times should be degraded by 20%.
C
C
CC
CCD
CP
H
T
CP
ΔI
I
CC
= I
= I
CCD
I
= Number of TTL Inputs at D
= Duty Cycle for TTL Inputs High
= Quiescent Current (I
C
= Clock Frequency for Register Devices (Zero for Non-Register Devices)
CC
= Number of Clock Inputs at f
QUIESCENT
= Dynamic Current caused by an Input Transition Pair (HLH or LHL)
CC
= Power Supply Current for a TTL High Input
+ ΔI
Parameter
Propagation Delay
xAx to xYx
Output Enable Time
Output Disable Time
Output Skew
CC
Quiescent Power Supply Current
TTL Inputs HIGH
Dynamic Power Supply
Current
Total Power Supply Current
+ I
D
H
INPUTS
N
T
+ I
(4)
CC
+ I
CCD
(4)
CCL
DYNAMIC
= 3.3V, +25°C ambient.
Parameter
(f
, I
CP
CCH
N
H
CP
CP
and I
/2 + fiNi)
CCZ
CC
(6)
)
or GND.
CC
formula. These limits are guaranteed but not tested.
CC
V
V
V
Outputs Open
xOE = GND
One Input Togging
50% Duty Cycle
V
Outputs Open
f
50% Duty Cycle
xOE = GND
One Bit Toggling
V
Outputs Open
f
50% Duty Cycle
xOE = GND
Sixteen BitsTogging
i
i
IN
CC
CC
CC
CC
= 10MHz
= 2.5MHz
= 3.3V±0.3V (normal range). For V
= V
= Max.
= Max.
= Max.
= Max.
CC
- 0.6V
Condition
R
C
L
L
= 500Ω
= 50pF
(3)
Test Conditions
(2)
4
CC
Min.
V
V
V
V
V
V
V
V
V
V
(1)
1.5
1.5
1.5
—
IN
IN
IN
IN
IN
IN
IN
IN
IN
IN
= 2.7 to 3.6V (extended range), all Propagation Delays and Enable/Disable
(3)
= V
= V
= V
= V
= V
= GND
= GND
= GND
= GND
= GND
FCT163244A
CC
CC
CC
CC
CC
- 0.6V
- 0.6V
Max.
4.8
6.2
5.6
0.5
INDUSTRIAL TEMPERATURE RANGE
Min.
—
—
—
—
—
—
(1)
Min.
1.5
1.5
1.5
—
Typ.
(3)
FCT163224C
0.5
0.5
50
2
2
2
(2)
Max.
3.3
0.8
0.8
3
30
75
Max.
(5)
4.1
5.8
5.2
0.5
(5)
MHz
Unit
µA/
mA
µ A
Unit
ns
ns
ns
ns