TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 472
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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ATA100
17.3.3.17. Host Reset Timer Register (C90h)
When executing Hard Reset using bit [11](ATA Hard Reset) of the System Control Register, this controller negates Reset
signals transmitted on the ATA Bus when the time this register sets elapses. This register sets this time value in 10 nsec
increments. The default for this register is 30 µsec (the ATA Spec. is 25 µsec).
You can also use this register as a timer for ATA soft reset. This timer is also invoked when Soft Reset using bit [2] of the
Device Control Register is issued. This Controller is configured to issue an interrupt simultaneous to when the set time is
reached.
Rev. 3.1 November 1, 2005
Bit 15
Bit 7
R/W
R/W
0
1
Bit 14
Bit 6
R/W
R/W
0
0
Bit 13
Bit 5
R/W
R/W
0
1
Figure 17-22 Host Reset Timer Register
Bit 12
Bit 4
R/W
R/W
0
1
RESET Timer
RESET Timer
17-18
Bit 11
Bit 3
R/W
R/W
1
1
Bit 10
Bit 2
R/W
R/W
0
0
Toshiba RISC Processor
Bit 9
Bit 1
R/W
R/W
1
0
Bit 8
Bit 0
R/W
R/W
1
0
TX4939
17
17
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