TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 289
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
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DMA
14.1. Features
The TX4939 contains two set of four-channel DMA Controller (DMAC0, DMAC1) that executes DMA (Direct Memory
Access) with memory and I/O devices.
The DMA Controller has the following characteristics.
DMAC has on-chip 8-channel DMA controller. Three channels are for transferring to memory and I/O devices. The other
channels are for internal resources (4 channels are dedicated for ACLC/I2S).
Rev. 3.1 November 1, 2005
<DMAC0, DMAC1>
□ Has four on-chip DMA channels
□ Supports Memory-Memory Copy modes that do not have address boundary limitations. Burst transfer of up
□ Supports Memory Fill mode that writes double-word data to the specified memory region
□ Supports Chained DMA Transfer
□ On-chip signed 24-bit address count up registers for both the source address and destination address
□ On-chip 26-bit Byte Count Register for each channel
□ One of two methods can be selected for determining access priority among multiple channels: Round Robin
□ Big Endian or Little Endian mode can be set separately for each channel
<DMAC0>
□ Supports external I/O devices with 8-, 16-, and 32-bit Data Bus widths and transfer between memory
□ Supports DMA on-chip Serial I/O Controllers, and NAND Flash Memory Controller
<DMAC1>
□ Supports DMA on-chip AC-Link Controllers
□ Supports DMA on-chip I2S Controllers
to eight double words is possible for each Read or Write operation.
or Fixed Priority
devices.
14-1
Chapter 14. DMA Controller
Toshiba RISC Processor
TX4939
14
14
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