TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 193
TX4939XBG-400
Manufacturer Part Number
TX4939XBG-400
Description
Manufacturer
Toshiba
Datasheet
1.TX4939XBG-400.pdf
(740 pages)
Specifications of TX4939XBG-400
Cpu Core
TX49/H4 90nm
Clock Mhz/max Mips
400/520
Inst./data Cache
32KB (4 Way)/32KB (4 Way)
Tlb
x
1cycle Mac
x
Volts (v)
1.25/2.5/3.3
Peripherals
DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
Companion Chip
TC86C001FG
Package
PGBA456
Available stocks
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Price
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872
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TX4939XBG-400
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TOSHIBA
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TX4939XBG-400
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20 000
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EBC
9.2.3.
Each of the four channels can use the Base Address field (EBCCRn.BA[35:20]) and the Channel Size field
(EBCCRn.CS[3:0]) of the External Bus Channel Control Register to map to any physical address.
In the above equation, paddr represents the accessed physical address, Mask[35:20] represents the address mask value
selected from Table 9-3 from the Channel Size field value, the ampersand (&) represents the AND operation, and the
exclamation mark (!) represents the Logical NOT for each bit.
Rev. 3.1 November 1, 2005
Address Mapping
A channel is selected when the following equation becomes True.
paddr[35:20] & !Mask[35:20] == BA[35:20] & !Mask[35:20]
CS[3:0]
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
0111
Channel Size
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
128 MB
256 MB
512 MB
16 MB
32 MB
64 MB
1 MB
2 MB
4 MB
8 MB
Table 9-3 Address Mask
9-3
0000_0000_0000_0000
0000_0000_0000_0001
0000_0000_0000_0011
0000_0000_0000_0111
0000_0000_0000_1111
0000_0000_0001_1111
0000_0000_0011_1111
0000_0000_0111_1111
0000_0000_1111_1111
0000_0001_1111_1111
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Address Mask[35:20]
Toshiba RISC Processor
TX4939
9
9
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