TX4939XBG-400 Toshiba, TX4939XBG-400 Datasheet - Page 275

• Manufacturer Part Number: TX4939XBG-400
• Manufacturer: Toshiba

Specifications of TX4939XBG-400

• Cpu Core: TX49/H4 90nm
• Clock Mhz/max Mips: 400/520
• Inst./data Cache: 32KB (4 Way)/32KB (4 Way)
• Tlb: x
• 1cycle Mac: x
• Volts (v): 1.25/2.5/3.3
• Peripherals: DDR, NAND, ATA, ETHERNET, SECURITY, FPU, MMU, SPI, I2S, I2C, PCI, VIDEO, UART, TIMER, RTC
• Companion Chip: TC86C001FG
• Package: PGBA456

TMR
13.4. Pulse Generator Mode
When in the Pulse Generator mode, use Compare Register A (TMCPRAn) and Compare Register B (TMCPRBn) to output
a particular period and particular duty square wave to the TIMER[n] signal. Setting the Timer Mode field (TMTCRn.TMODE)
of the Timer Control Register to “01” sets the timer to the Pulse Generator mode. Timer 0 and Timer 1 can be used, but Timer
2 cannot.
The initial state of the TIMER[n] signal can be set by the Flip Flop Default bit (TMPGMRn.FFI) of the Pulse Generator Mode
Register.
The TIMER[n] output signal reverses when the counter value matches the value set in Compare Register A (TMCPRAn).
The TIMER[n] output signal reverse again, clearing the counter when the counter continues counting and the value set in
Compare Register B (TMCPRBn) and the counter value match. Consequently, a value greater than that in Compare
Register A (TMCPRAn) must not be set in Compare Register B (TMCPRBn).
Interrupts can be generated in the Pulse Generator mode as well. However, this is not standard practice.
The Pulse Generator TMCPRA Status bit (TMTISRn.TPIAS) of the Timer Interrupt Status Register is set when the count
value matches the value of Compare Register A (TMCPRAn). Timer interrupts are generated when the TMCPRA Interrupt
Enable bit (TMPGMRn.TPIAE) of the Pulse Generator Mode Register is set.
Similarly, the Pulse Generator TMCPRB Status bit (TMTISRn.TPIBS) of the Timer Interrupt Status Register is set when the
count value matches the value of Compare Register B (TMCPRBn). Timer interrupts are generated when the TMCPRB
Interrupt Enable bit (TMPGMRn.TPIBE) of the Pulse Generator Mode Register is set.
Rev. 3.1 November 1, 2005
Compare Value
Compare Value
TMCPRAn
TMCPRBn
Count Value
TCE
TIMER [n]
Figure 13-5 Operation Example of the Pulse Generator Mode
TMODE = 01 (Pulse Generator Mode), CCS = 0 (Internal Clock)
FFI = 1 (Initial High), CRE = 0 (Counter not Reset)
13-7
(Count Disable)
TCE = 0
Toshiba RISC Processor
Time
R e v 1 . 0 0
TX4939
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