TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 201

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

15.3 Function
SIO2SR<SEF>
SO2 pin
SIO2SR<TXF>
SIO2CR<SIOS>
SIO2SR<SIOF>
SCK2 pin outout
INTSIO2
interrupt
request
SIO2TDB
(2)
(3)
Figure 15-6 Example of Internal Clock and MSB Transmit Mode
Writing transmit
data A
stops to “H” level by an automatic-wait function when all of the bit set in the SIO2TDB has been
transmitted. Automatic-wait function is released by writing a transmit data to SIO2TDB. Then, trans-
mit operation is restarted after maximum 1-cycle of serial clock.
SIO2SR<TXF> “1”, the next data is continuously transferred after transmission of previous data.
SIO2TDB before the shift operation of the next data begins.
tion is started. Then, INTSIO2 interrupt request is generated after SIO2SR<TXERR> is set to “1”.
During the transmit operation
When data is written to SIO2TDB, SIO2SR<TXF> is cleared to “0”.
In internal clock operation, in case a next transmit data is not written to SIO2TDB, the serial clock
When the next data is written to the SIO2TDB before termination of previous 8-bit data with
In external clock operation, after SIO2SR<TXF> is set to “1”, the transmit data must be written to
If the transmit data is not written to SIO2TDB, transmit error occurs immediately after shift opera-
Stopping the transmit operation
There are two ways for stopping transmits operation.
A
• The way of clearing SIO2CR<SIOS>.
• The way of setting SIO2CR<SIOINH>.
When SIO2CR<SIOS> is cleared to “0”, transmit operation is stopped after all transfer of the
data is finished. When transmit operation is finished, SIO2SR<SIOF> is cleared to “0” and
SO2 pin is kept in high level.
In external clock operation, SIO2CR<SIOS> must be cleared to “0” before SIO2SR<SEF> is
set to “1” by beginning next transfer.
Transmit operation is stopped immediately after SIO2CR<SIOINH> is set to “1”. In this
case, SIO2CR<SIOS>, SIO2SR register, SIO2RDB register and SIO2TDB register are ini-
tialized.
A7
Writing transmit
data B
A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1
Start shift
operation
B
Page 184
Start shift
operation
B0
Automatic wait
Writing transmit
data C
C
C7
Start shift
operation
C6 C5 C4 C3 C2 C1 C0
Clearing SIOS
TMP86PM49UG