TMP86xy49UG/F/NG Toshiba, TMP86xy49UG/F/NG Datasheet - Page 111

• Manufacturer Part Number: TMP86xy49UG/F/NG
• Manufacturer: Toshiba

Specifications of TMP86xy49UG/F/NG

• Package: LQFP64/QFP64/SDIP64
• Rom Types (m=mask,p=otp,f=flash): M/P/F
• Rom Size: 16/32/60
• Ram Size: 512/1K/2K
• Driver Led: 13
• Driver Lcd: -
• Spi/sio Channels: 2
• Uart/sio Channels: 2
• I2c/sio Channels: 1
• High-speed Serial Output: -
• Adc 8-bit Channels: -
• Adc 10-bit Channels: 16
• Da Converter Channels: -
• Timer Counter 18-bit Channel: -
• Timer Counter 16-bit Channel: 2
• Timer Counter 8-bit Channel: 4
• Motor Channels: -
• Watchdog Timer: Y
• Dual Clock: Y
• Clock Gear: -
• Number Of I/o Ports: 56
• Power Supply (v): 4.5 to 5.5

9.2 Control
9.2 Control
(0025H,
(0023H)
TC2DR
0024H)
TC2CR
TC2CK
(TC2DR).
TC2M
TC2S
The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register 2
Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care
Note 2: When writing to the Timer Register 2 (TC2DR), always write to the lower side (TC2DRL) and then the upper side
Note 3: The timer register 2 (TC2DR) uses the value previously set in it for coincidence detection until data is written to the upper
Note 4: Set the mode and source clock when the TC2 stops (TC2S = 0).
Note 5: Values to be loaded to the timer register must satisfy the following condition.
Note 6: If a read instruction is executed for TC2CR, read data of bit 7, 6 and 1 are unstable.
Note 7: The high-frequency clock (fc) canbe selected only when the time mode at SLOW2 mode is selected.
Note 8: On entering STOP mode, the TC2 start control (TC2S) is cleared to "0" automatically. So, the timer stops. Once the STOP
TC2 start control
TC2 source clock select
TC2 operating mode
select
(TC2DRH) in that order. Writing to only the lower side (TC2DRL) or the upper side (TC2DRH) has no effect.
side (TC2DRH) after writing data to the lower side (TC2DRL).
TC2DR > 1 (TC2DR
mode has been released, to start using the timer counter, set TC2S again.
15
7
Unit : [Hz]
14
6
(Initial value: 1111 1111 1111 1111)
13
TC2DRH (0025H)
15
TC2S
5
to TC2DR
12
0:Stop and counter clear
1:Start
0:Timer/event counter mode
1:Window mode
000
001
010
100
101
011
110
111
11
4
11
> 1 at warm up)
DV7CK = 0
10
TC2CK
fc/2
fc/2
fc/2
fc/2
fs
–
NORMAL1/2, IDLE1/2 mode
3
23
13
8
3
9
Page 94
2
8
External clock (TC2 pin input)
7
DV7CK = 1
1
fs/2
fs/2
fc/2
fc/2
fs
–
15
Reserved
5
8
3
6
TC2M
0
5
TC2DRL (0024H)
(Initial value: **00 00*0)
Divider
DV21
DV11
DV6
DV1
4
–
–
R/W
3
fc (Note7)
SLOW1/2
mode
fs/2
fs/2
–
–
–
15
5
2
TMP86PM49UG
SLEEP1/2
mode
fs/2
1
fs/2
–
–
–
–
15
5
0
R/W
R/W
R/W