74LVC2G125DC,125 NXP Semiconductors, 74LVC2G125DC,125 Datasheet - Page 10
![IC BUS BUFF DVR TRI-ST DL 8VSSOP](/photos/6/94/69485/8-vssop_sot765-1_sml.jpg)
74LVC2G125DC,125
Manufacturer Part Number
74LVC2G125DC,125
Description
IC BUS BUFF DVR TRI-ST DL 8VSSOP
Manufacturer
NXP Semiconductors
Series
74LVCr
Datasheet
1.74LVC2G125DC125.pdf
(22 pages)
Specifications of 74LVC2G125DC,125
Package / Case
US8, 8-VSSOP
Logic Type
Buffer/Line Driver, Non-Inverting
Number Of Elements
2
Number Of Bits Per Element
1
Current - Output High, Low
32mA, 32mA
Voltage - Supply
2 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Mounting Type
Surface Mount
Logic Family
LVC
Number Of Channels Per Chip
2
Polarity
Non-Inverting
Supply Voltage (max)
5.5 V
Supply Voltage (min)
1.65 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
High Level Output Current
- 32 mA
Input Bias Current (max)
40 uA
Low Level Output Current
32 mA
Minimum Operating Temperature
- 40 C
Output Type
3-State
Propagation Delay Time
2.7 ns (Typ) @ 2.7 V or 2.3 ns (Typ) @ 3 V to 3.6 V or 1.9 ns (Typ) @ 4.5 V to 5.5 V
Number Of Lines (input / Output)
2 / 2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
74LVC2G125DC-G
74LVC2G125DC-G
935274507125
74LVC2G125DC-G
935274507125
NXP Semiconductors
Table 10.
74LVC2G125
Product data sheet
Supply voltage
V
1.65 V to 1.95 V
2.3 V to 2.7 V
2.7 V
3.0 V to 3.6 V
4.5 V to 5.5 V
Fig 9.
CC
Test data is given in
Definitions for test circuit:
R
C
R
V
Test circuit for measuring switching times
L
L
T
EXT
Test data
= Load resistor.
= Load capacitance including jig and probe capacitance.
= Termination resistance should be equal to output impedance Z
= Test voltage for switching times.
Table
Input
V
V
V
2.7 V
2.7 V
V
I
CC
CC
CC
10.
negative
positive
pulse
pulse
GENERATOR
0 V
0 V
V
V
I
I
PULSE
All information provided in this document is subject to legal disclaimers.
t
≤ 2.0 ns
≤ 2.0 ns
≤ 2.5 ns
≤ 2.5 ns
≤ 2.5 ns
r
90 %
10 %
, t
f
Rev. 11 — 9 September 2010
t
t
r
f
V
V
V
M
M
10 %
90 %
I
Load
C
30 pF
30 pF
50 pF
50 pF
50 pF
L
R T
V
DUT
t
t
W
W
CC
R
1 kΩ
500 Ω
500 Ω
500 Ω
500 Ω
o
L
of the pulse generator.
V
O
V
V
M
M
t
t
r
f
C L
001aae235
V
t
open
open
open
open
open
V
PLH
Dual bus buffer/line driver; 3-state
EXT
EXT
, t
R L
R L
PHL
74LVC2G125
t
GND
GND
GND
GND
GND
PZH
, t
PHZ
© NXP B.V. 2010. All rights reserved.
t
2V
2V
6 V
6 V
2V
PZL
CC
CC
CC
, t
PLZ
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