TDA18254HN/C1,518 NXP Semiconductors, TDA18254HN/C1,518 Datasheet - Page 34

• Manufacturer Part Number: TDA18254HN/C1,518
• Description: IC CABLE TUNER DGTL 48HVQFN
• Manufacturer: NXP Semiconductors
• Type: Tunerr

Specifications of TDA18254HN/C1,518

• Mounting Type: Surface Mount
• Package / Case: 48-VQFN Exposed Pad, 48-HVQFN, 48-SQFN, 48-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Applications: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 935289589518

NXP Semiconductors
SC16C852V
Product data sheet
7.15 Transmit Interrupt Level register (TXINTLVL)
7.16 Receive Interrupt Level register (RXINTLVL)
Table 26.
[1]
This 8-bit register is used store the transmit FIFO trigger levels used for DMA and
interrupt generation. Trigger levels from 1 to 128 can be programmed with a granularity
of 1.
Table 27.
[1]
This 8-bit register is used store the receive FIFO trigger levels used for DMA and interrupt
generation. Trigger levels from 1 to 128 can be programmed with a granularity of 1.
Table 28
Table 28.
[1]
Cont-3
1
X
X
X
1
0
1
Bit
7:0
Bit
7:0
When using a software flow control the Xon/Xoff characters cannot be used for data transfer.
For 32-byte FIFO mode, refer to
For 32-byte FIFO mode, refer to
Table 27
TXINTLVL[7:0]
RXINTLVL[7:0]
Symbol
Symbol
shows trigger level register bit settings.
Cont-2
1
X
X
X
0
1
1
Software flow control functions
TXINTLVL register bits description
RXINTLVL register bits description
shows trigger level register bit settings.
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
All information provided in this document is subject to legal disclaimers.
Cont-1
X
0
1
0
1
1
1
Rev. 5 — 21 January 2011
This register stores the programmable transmit interrupt trigger levels for
This register stores the programmable receive interrupt trigger levels for
Description
128-byte FIFO mode.
Description
128-byte FIFO mode.
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
0x00 = trigger level is set to 1
0x01 = trigger level is set to 1
...
0x80 = trigger level is set to 128
Cont-0
X
0
0
1
1
1
1
Section 7.3 “FIFO Control Register
Section 7.3 “FIFO Control Register
TX, RX software flow controls
Transmit Xon1 and Xon2/Xoff1 and Xoff2
No receive flow control
Receiver compares Xon1/Xoff1
Receiver compares Xon2/Xoff2
Transmit Xon1/Xoff1
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon2/Xoff2
Receiver compares Xon1 or Xon2, Xoff1 or Xoff2
Transmit Xon1 and Xon2, Xoff1 and Xoff2
Receiver compares Xon1 and Xon2, Xoff1 and Xoff2
[1]
[1]
[1]
…continued
(FCR)”.
(FCR)”.
SC16C852V
© NXP B.V. 2011. All rights reserved.
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