LMH1983SQE/NOPB National Semiconductor, LMH1983SQE/NOPB Datasheet - Page 26

• Manufacturer Part Number: LMH1983SQE/NOPB
• Description: IC VID CLK GEN MULTI RATE 40LLP
• Manufacturer: National Semiconductor
• Type: Clock Generatorr

Specifications of LMH1983SQE/NOPB

• Applications: Video Equipment
• Mounting Type: Surface Mount
• Package / Case: 40-LLP
• Leaded Process Compatible: Yes
• Rohs Compliant: Yes
• Interface Type: I2C
• Supply Voltage (max): 3.3 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Peak Reflow Compatible (260 C): Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: LMH1983SQETR

www.national.com
second loop in which the phase of TOF1 and V
pared, and depending upon the mode of the device, this loop
can drive the VCXO control voltage to slew the output clocks
into alignment.
PLL1 Loop Response Design
Equations
The primary loop takes the reference applied to the H
divides that by R (stored in registers 0x29 and 0x2A), and then
compares it in phase and frequency to the output of the ex-
ternal VCXO divided by N (stored in registers 0x2B and 0x2C)
The PFD then generates output pulses which are integrated
via an external loop filter which drives the control voltage of
the external VCXO (refer to PLL1 Block Diagram). Assuming
a topology for the loop filter which is similar to that shown in
the PLL1 block diagram, the bandwidth of the PLL is deter-
mined by:
BW
Where
•
•
•
•
Under normal operation, several of these parameters are set
by the device automatically, for example the charge pump
current and the value of 'FB_DIV'. When the input reference
format changes, both N and the charge pump current are up-
R
K
Pull_range*27 MHz/Vin_Range. For the VCXO used in the
typical interface circuit (Mfgr: CTS, P/N
357LB3C027M0000): L
(3.0V-0.3V) = 1000 Hz/V
I
FB_DIV is the divide ratio of the PLL, which is set by the
R and N register values, this will be equal to the number
of 27 MHz clock pulses in one H
value will be 1716
PLL1
CP1
VCO
S
is the series resistor value in the external loop filter
= R
is the current from the PLL1 chargepump
is the nominal 27 MHz VCXO gain in Hz/V. K
S
x K
VCO
x I
CP1
/FB_DIV
VCO
=100 ppm*27 MHz /
IN
period. For NTSC this
IN
are com-
IN
PLL1 Block Diagram
VCO
input,
=
26
dated, N is changed to allow for lock to the new reference,
and the charge pump current is adjusted to try to maintain
constant loop bandwidth.
It should be noted that this bandwidth calculation is an ap-
proximation, and does not take into account the effects of the
damping factor or the second pole introduced by C
At frequencies far above the –3dB loop bandwidth the closed-
loop frequency response of PLL1 will roll off at about –40dB/
decade, which is useful for attenuating input jitter at frequen-
cies above the loop bandwidth. Near the –3dB corner fre-
quency, the roll-off characteristic will depend on other factors,
such as damping factor and filter order.
To prevent output jitter due to the modulation of the VCXO by
the PLL's phase comparison frequency the bandwidth needs
to meet the following criterion:
•
PLL1s damping factor can be approximated by:
•
Where C
Typically, DF is targeted to be between 1/
yield a good trade off between lock time and reference spur
attenuation. DF is related to the phase margin, which is a
measure of the PLL stability.
There is a second parallel capacitor, C
filter the reference spurs introduced by the PLL which may
modulate the VCXO control voltage, leading to jitter. The fol-
lowing relationship should be used to determine C
•
The PLL loop gain, K can be calculated as:K = I
FB_DIV
Therefore Bandwidth and Damping Factor can be expressed
in terms of K:
•
•
BW (27 MHz / FB_DIV ) / 20
DF = (R
C
BW = R
DF = (R
P
≈
C
S
S
/20
is the value of the series capacitor (in Farads)
S
S
S
*K
/2)
/2)*
√
√
(I
(C
CP1
S
*K)
*C
S
*K
VCO
/FB_DIV)
P
√
which is needed to
2 and 1 which will
30085144
P
CP1
P
:
.
*K
VCO
/