LMH1983SQE/NOPB National Semiconductor, LMH1983SQE/NOPB Datasheet - Page 16

IC VID CLK GEN MULTI RATE 40LLP

LMH1983SQE/NOPB

Manufacturer Part Number
LMH1983SQE/NOPB
Description
IC VID CLK GEN MULTI RATE 40LLP
Manufacturer
National Semiconductor
Type
Clock Generatorr
Datasheet

Specifications of LMH1983SQE/NOPB

Applications
Video Equipment
Mounting Type
Surface Mount
Package / Case
40-LLP
Leaded Process Compatible
Yes
Rohs Compliant
Yes
Interface Type
I2C
Supply Voltage (max)
3.3 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Peak Reflow Compatible (260 C)
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
LMH1983SQETR

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LMH1983SQE/NOPB
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ADD
0x16
0x17
0x18
0x19
0x1A
Name
LOR Control –
Holdover Sampled
Voltage MSB
LOR Control –
Holdover Sampled
Voltage LSB
LOR Control Free-run
Control Voltage MSB
LOR Control – Free-
run Control Voltage
LSB
LOR Control – ADC &
DAC Disable
Bits
7:2
1:0
7:0
7:2
1:0
7:0
7:2
1
0
Field
RSVD
VC_Hold_MSB
VC_Hold_LSB
RSVD
VC_Free_MSB
VC_Free_LSB
RSVD
ADC_Disable
DAC_Disable
16
R/W
R/W
R/W
R/W
R/W
R
R
Default
10
NA
01
0xFF
0
0
Description
Reserved
The VC_Hold[9:0] input signal changes
rather slowly. For synchronization, it should
be sampled on consecutive 27 MHz clocks
until two identical values are found. This
value will be saved as VC_Hold_sampled
[9:0].
Whenever the VC_Hold[9:8] register is read,
VC_Hold_sampled[9:8] is returned, and
VC_Hold[7:0] will memorize the current value
of VC_Hold_sampled[7:0] (to be read at a
later time).
This scheme allows a coherent 10-bit value
to be read.
Returns a synchronized snapshot of the
VC_Hold[9:8] (MSB).
The VC_Hold[9:0] input signal changes
rather slowly. For synchronization, it should
be sampled on consecutive 27 MHz clocks
until two identical values are found. This
value will be saved as VC_Hold_sampled
[9:0].
Whenever the VC_Hold[9:8] register is read,
VC_Hold_sampled[9:8] is returned, and
VC_Hold[7:0] will memorize the current value
of VC_Hold_sampled[7:0] (to be read at a
later time).
This scheme allows a coherent 10-bit value
to be read.
Returns a synchronized snapshot of the
VC_Hold[7:0] (LSB)
Reserved
Free-run Control Volage (VC_Free[9:0]) is
the voltage asserted on VC_LPF pin in free-
run mode.
Writing will change the MSB (VC_Free[9:8])
Free-run Control Volage (VC_Free[9:0]) is
the voltage asserted on VC_LPF pin in free-
run mode.
Writing will change the LSB (VC_Free[7:0])
Reserved
Directly controls the ADC_Disable output
port.
0 = enable holdover ADC
1 = disable holdover ADC
Directly controls the DAC_Disable output
port.
0 = enable Free-run/Holdover DAC
1 = disable Free-run/Holdover DAC

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