ISL98001CQZ-140 Intersil, ISL98001CQZ-140 Datasheet - Page 25

• Manufacturer Part Number: ISL98001CQZ-140
• Description: IC TRPL VIDEO DIGITIZER 128-MQFP
• Manufacturer: Intersil
• Type: Video Digitizerr

Specifications of ISL98001CQZ-140

• Applications: Digital TV, Displays, Digital KVM, Graphics Processing
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

may be significantly smaller, sometimes 300mV
In these cases the sync slicer will continue to operate
correctly, but the TriLevel Detect bit may not be set. Trilevel
detection accuracy can be enhanced by polling the trilevel
bit multiple times. If HSYNC is inactive, SOG is present, and
the TriLevel Sync Detect bit is read as a 1, there is a high
likelihood there is trilevel sync.
CSYNC Present
If a composite sync source (either CSYNC on HSYNC or
SOG) is selected through bits 3 and 4 of register 0x05, the
CSYNC Present bit in register 0x01 should be set. CSYNC
Present detects the presence of a low frequency, repetitive
signal inside HSYNC, which indicates a VSYNC signal. The
CSYNC Present bit should be used to confirm that the signal
being received is a reliable composite sync source.
SYNC Output Signals
The ISL98001 has 2 pairs of HSYNC and VSYNC output
signals, HSYNC
VS
HSYNC
incoming sync signals; no synchronization is done. These
signals are used for mode detection
HS
and are synchronized to the output DATACLK and the digital
pixel data on the output databus. HS
the start of a new line of digital data. VS
most applications.
Both HSYNC
separator function) remain active in power-down mode. This
allows them to be used in conjunction with the Sync Status
registers to detect valid video without powering up the
ISL98001.
HSYNC
HSYNC
HSYNC
incoming signal’s period, polarity, and width to aid in mode
detection. HSYNC
sync signal: either horizontal or composite sync. If a SOG input
is selected, HSYNC
including the VSYNC portion, pre-/post-equalization pulses if
present, and Macrovision pulses if present. HSYNC
remains active when the ISL98001 is in power-down mode.
HSYNC
VSYNC
VSYNC
incoming VSYNC
original VSYNC period, polarity, and width to aid in mode
detection. If a SOG input is selected, this signal will output
the VSYNC signal extracted by the ISL98001’s sync slicer.
Extracted VSYNC will be the width of the embedded VSYNC
pulse plus pre- and post-equalization pulses (if present).
OUT
OUT
.
OUT
IN
OUT
OUT
OUT
and VS
OUT
OUT
or SOG
is an unmodified, buffered version of the incoming
is generally used for mode detection.
is an unmodified, buffered version of the
and VSYNC
OUT
OUT
OUT
OUT
IN
IN
and VSYNC
OUT
signal of the selected channel, with the
signal of the selected channel, with the
are generated by the ISL98001’s logic
and VSYNC
will be the same format as the incoming
will output the entire SOG signal,
OUT
25
are buffered versions of the
OUT
OUT
(including the sync
OUT
, and HS
OUT
is used to signal
is not needed in
OUT
P-P
OUT
and
or less.
ISL98001
Macrovision pulses from an NTSC DVD source will lengthen
the width of the VSYNC pulse. Macrovision pulses from
other sources (PAL DVD or videotape) may appear as a
second VSYNC pulse encompassing the width of the
Macrovision. See the Macrovision section for more
information. VSYNC
function) remains active in power-down mode. VSYNC
is generally used for mode detection, start of field detection,
and even/odd field detection.
HS
HS
synchronized to the output DATACLK and the digital pixel
data on the output databus. Its trailing edge is aligned with
pixel 0. Its width, in units of pixels, is determined by register
0x19, and its polarity is determined by register 0x18[7]. As
the width is increased, the trailing edge stays aligned with
pixel 0, while the leading edge is moved backwards in time
relative to pixel 0. HS
start of a new line of pixels.
The HS
HS
period times the value in this register. In the 48 bit output
mode (register 0x18[0] = 1), or the YPbPr input mode
(register 0x05[2] = 1), the HS
pixel clock (1 DATACLK) increments (see Table 8).
VS
VS
synchronized to the output DATACLK and the digital pixel
data on the output databus. Its leading and trailing edges are
aligned with pixel 7 (8 pixels after HSYNC trailing edge). Its
width, in units of lines, is equal to the width of the incoming
VSYNC (See the VSYNC
determined by register 0x18[6]. Note: This output is not
needed in most applications. Intersil strongly discourages
using this signal - use VSYNC
0x19 VALUE
REGISTER
OUT
OUT
OUT
OUT
OUT
0
1
2
3
4
5
6
7
OUT
is generated by the ISL98001’s control logic and is
is generated by the ISL98001’s control logic and is
pulse. The pulse width is nominally 1 pixel clock
Width register (0x19) controls the width of the
24-BIT MODE,
TABLE 8. HS
RGB
OUT
OUT
0
1
2
3
4
5
6
7
HS
OUT
(including the sync separator
OUT
is used by the scaler to signal the
OUT
WIDTH (PIXEL CLOCKS)
OUT
description). Its polarity is
24-BIT MODE,
OUT
width is incremented in 2
YPbPr
instead.
WIDTH
1
1
3
3
5
5
7
7
September 21, 2010
ALL 48-BIT
MODES
0
0
2
2
4
4
6
6
FN6148.5
OUT