ISL98001CQZ-140 Intersil, ISL98001CQZ-140 Datasheet - Page 21

• Manufacturer Part Number: ISL98001CQZ-140
• Description: IC TRPL VIDEO DIGITIZER 128-MQFP
• Manufacturer: Intersil
• Type: Video Digitizerr

Specifications of ISL98001CQZ-140

• Applications: Digital TV, Displays, Digital KVM, Graphics Processing
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the HSYNC input, or composite sync from a Sync-On-Green
(SOG) signal embedded on the Green video input. The
ISL98001 has SYNC activity detect functions to help the
firmware determine which sync source is available.
Macrovision
The ISL98001 automatically detects the presence of
Macrovision-encoded video. When Macrovision is detected,
it generates a mask signal that is ANDed with the incoming
SOG CSYNC signal to remove the Macrovision before the
HSYNC goes to the PLL. No additional programming is
required to support Macrovision.
If desired (it is never necessary in normal operation), this
function can be disabled by setting the Sync Mask Disable
(register 0x05 bit 6) to a 1.
The mask signal is also applied to the HSYNC
When Sync Mask Disable = 0, any Macrovision present on
the incoming sync will not be visible on HSYNC
application requires the Macrovision pulses to be visible on
HSYNC
0x05 bit 7).
Headswitching from Analog Videotape Signals
Occasionally this AFE may be used to digitize signals
coming from analog videotape sources. The most common
example of this is a Digital VCR (which for best signal quality
CLOCKINV
HSYNC
HSYNC
VSYNC
VSYNC
OUT
XTAL
SOG
SOG
XTAL
, set the HSYNC
OUT
IN
IN
IN
IN
IN
IN
IN
IN
1
1
1
2
2
2
0x04[3:0]
0x03[6:4]
0x04[3:0]
0x03[2:0]
HSYNC2
HSYNC1
SLICER
SLICER
SLICER
SLICER
SOG
SOG
OUT
21
POLARITY 0x02[5:0]
ACTIVITY 0x01[6:0]
÷2
Mask Disable bit (register
DETECT
&
0: ÷1
0x13
1: ÷2
[6]
OUT
OUT
0x05[0]
VGA1
VGA2
signal.
. If the
0:
1:
FIGURE 8. SYNC FLOW
SOG
VSYNC
HSYNC
GENERATION
0x0E through 0x13
ISL98001
0x11, 0x12
IN
COAST
IN
IN
PLL
SOURCE
HSYNC
0x05[4:3]
CSYNC
00, 10,
SOG
11:
01:
IN
IN
would be connected to this AFE with a component YPbPr
connection). If the digital VCR is playing an older analog
VHS tape, the sync signals from the VCR may contain the
worst of the traditional analog tape artifacts: headswitching.
Headswitching is traditionally the enemy of PLLs with large
capture ranges, because a headswitch can cause the
HSYNC period to change by as much as ±90%. To the PLL,
this can look like a frequency change of -50% to greater than
+900%, causing errors in the output frequency (and
obviously the phase) to change. Subsequent HSYNCs have
the correct, original period, but most analog PLLs will take
dozens of lines to settle back to the correct frequency and
phase after a headswitch disturbance. This causes the top of
the image to “tear” during normal playback. In “trick modes”
(fast forward and rewind), the HSYNC signal has multiple
headswitch-like discontinuities, and many PLLs never settle
to the correct value before the next headswitch, rendering
the image completely unintelligible.
Intersil’s DPLL has the capability to correct large phase
changes almost instantly by maximizing the phase error gain
while keeping the frequency gain relatively low. This is done
by changing the contents of register 0x1C to 0x4C. This
increases the phase error gain to 100%. Because a phase
setting this high will slightly increase jitter, the default setting
(0x49) for register 0x1C is recommended for all other sync
sources.
Pixel Data
from AFE
HS
PIXCLK
SPLITTER
SYNC
24
VSYNC
VSYNC
SYNC
SPLTR
0x05[3]
TYPE
SYNC
Formatter
1:
0:
Output
0x18,
0x19,
0x1A
IN
XTALCLOCK
September 21, 2010
VSYNC
HSYNC
DATACLK
DATACLK
R
R
G
G
B
B
HS
VS
P
S
P
S
P
S
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
[7:0]
OUT
OUT
OUT
OUT
OUT
FN6148.5