73S1210F Maxim, 73S1210F Datasheet
73S1210F
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73S1210F Summary of contents
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... Simplifying System Integration™ GENERAL DESCRIPTION The 73S1210F is a versatile and economical CMOS System-on-Chip device intended for smart card reader applications. The circuit is built around an 80515 high- performance core; it features primarily an ISO-7816 / EMV interface and a generic asynchronous serial interface. Delivered with turnkey Teridian embedded firmware, it ...
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... Data Sheet FEATURES 80515 Core: • 1 clock cycle per instruction (most instructions) • CPU clocked up to 24MHz • 32KB Flash memory (lockable) • 2kB XRAM (User Data Memory) • 256 byte IRAM • Hardware watchdog timer Oscillators: • Single low-cost 6MHz to 12MHz crystal • ...
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... Package Pin Designation ............................................................................................................... 120 5.1 68-pin QFN Pinout ................................................................................................................... 120 5.2 44-pin QFN Pinout ................................................................................................................... 121 6 Packaging Information ................................................................................................................... 122 6.1 68-Pin QFN Package Outline .................................................................................................. 122 6.2 44-Pin QFN Package Outline .................................................................................................. 123 7 Ordering Information ...................................................................................................................... 124 8 Related Documentation .................................................................................................................. 124 9 Contact Information ........................................................................................................................ 124 Revision History ...................................................................................................................................... 125 Rev. 1.4 Table of Contents 73S1210F Data Sheet 3 ...
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... Figure 40: Smart Card I/O Circuit ............................................................................................................. 118 Figure 41: PRES Input Circuit ................................................................................................................... 118 Figure 42: PRESB Input Circuit ................................................................................................................ 118 Figure 43: ON_OFF Input Circuit .............................................................................................................. 119 Figure 44: 73S1210F 68 QFN Pinout ....................................................................................................... 120 Figure 45: 73S1210F 44 QFN Pinout ....................................................................................................... 121 Figure 46: 73S1210F 68 QFN Mechanical Drawing ................................................................................. 122 Figure 47: 73S1210F 44 QFN Package Drawing ..................................................................................... 123 4 DS_1210F_001 Rev. 1.4 ...
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... Table 48: UDIR Control Bit ......................................................................................................................... 49 Table 49: Selectable Controls Using the UxIS Bits ..................................................................................... 49 Table 50: The USRIntCtl1 Register ............................................................................................................ 50 Table 51: The USRIntCtl2 Register ............................................................................................................ 50 Table 52: The USRIntCtl3 Register ............................................................................................................ 50 Table 53: The USRIntCtl4 Register ............................................................................................................ 50 Table 54: The ACOMP Register ................................................................................................................. 51 Table 55: The INT6Ctl Register .................................................................................................................. 52 Table 56: The LEDCtl Register ................................................................................................................... 53 Rev. 1.4 73S1210F Data Sheet 5 ...
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... Data Sheet Table 57: The DAR Register ....................................................................................................................... 57 Table 58: The WDR Register ...................................................................................................................... 57 Table 59: The SWDR Register ................................................................................................................... 58 Table 60: The RDR Register ....................................................................................................................... 58 Table 61: The SRDR Register .................................................................................................................... 59 Table 62: The CSR Register ....................................................................................................................... 59 Table 63: The INT6Ctl Register .................................................................................................................. 60 Table 64: The KCOL Register ..................................................................................................................... 64 Table 65: The KROW Register ................................................................................................................... 64 Table 66: The KSCAN Register .................................................................................................................. 65 Table 67: The KSTAT Register ...
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... CORE IRAM INTERFACE 256B ALU WATCH- PMU DOG DATA TIMER XRAM PORTS 2KB ISR SERIAL PERIPHERAL INTERFACE and SFR LOGIC 73S1210F Data Sheet ON_OFF OFF_REQ POWER REGULATION VDD AND VCC CONTROL VCC LOGIC GND RST CLK SMART CARD I/O ISO INTERFACE AUX1 ...
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... Data Sheet 1 Hardware Description 1.1 Pin Description Pin Name X12IN X12OUT ROW(5: COL(4: USR(7: SCL ...
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... Power control pin. Connected to normally open SPST switch to ground. Closing switch for duration greater than debounce period will turn 73S1210F on. If 73S1210F is on, closing switch will flag the 73S1210F the off state. Firmware will control when the power is shut down. Figure 33 Digital output. If ON_OFF switch is closed (to ground) for debounce duration and circuit is “ ...
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... Reset input, positive assertion. Resets logic and registers to default condition. Note: to insure proper reset operation after V is turned on by application activation of the ON/OFF switch, external reset circuitry must generate a proper reset signal to the 73S1210F. This can be accomplished via a simple RC network. section. DS_1210F_001 power or BUS ...
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... DS_1210F_001 1.2 Hardware Overview The 73S1210F single smart card controller integrates all primary functional blocks required to implement a smart card reader. Included on chip are an 8051-compatible microprocessor (MPU) which executes up to one instruction per clock cycle (80515), a fully integrated IS0 7816 compliant smart card interface, expansion smart card interface, serial interface, I2C interface keypad interface, RAM, FLASH memory, and a variety of I/O pins ...
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... Data Sheet specific SFR registers in the proper sequence. These special pattern/sequence requirements prevent inadvertent erasure of the flash memory. The mass erase sequence is: 1. Write 1 to the FLSH_MEEN bit in the 2. Write pattern 0xAA to ERASE Note: The mass erase cycle can only be initiated when the ICE port is enabled. ...
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... The next 16 bytes form a block of bit-addressable memory space at bit addresses 0x00- 0x7F. All of the bytes in the lower 128 bytes are accessible through direct or indirect addressing. shows the internal data memory map. Rev. 1.4 Description to PGADDR @ SFR 0xB7. to FLSH_MEEN @ SFR 0xB2 and the debug port must be enabled. 73S1210F Data Sheet Table 4 13 ...
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... Data Sheet Address 0xFF Special Function Registers (SFRs) 0x80 0x7F Byte-addressable area 0x30 0x2F Byte or bit-addressable area 0x20 0x1F 0x00 External Data Memory: While the 80515 can address up to 64KB of external data memory in the space from 0x0000 to 0xFFFF, only the memory ranges shown in Figure 2 contain physical memory. The 80515 writes into external data memory when the MPU executes a MOVX @Ri,A or MOVX @DPTR,A instruction ...
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... The second data pointer may not be supported by certain compilers. Rev. 1.4 Use Peripheral Control Registers (128b) Smart Card Control (384b) – XRAM External Data Memory Figure 2: Memory Map 73S1210F Data Sheet Use Address Indirect Access Direct Access 0xFF Byte RAM 0x80 0x7F Byte RAM 0x48 ...
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... Data Sheet 1.4 Program Security Two levels of program and data security are available. Each level requires a specific fuse to be blown in order to enable or set the specific security mode. Mode 0 security is enabled by setting the SECURE bit (bit 6 of SFR register FLSHCTL 0xB2). Mode 0 limits the ICE interface to only allow bulk erase of the flash program memory. All other ICE operations are blocked. This guarantees the security of the user’ ...
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... The user can force this pin high during boot sequence time to indicate to firmware that sec mode 1 is desired. R/W Bit 1 (SECSET1): See the Program Security section. R/W Bit 0 (SECSET0): See the Program Security section. Rev. 1.4 Table 5: Program Security Registers Description 73S1210F Data Sheet 17 ...
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... SP Only a few addresses are used, the others are not implemented. SFRs specific to the 73S1210F are shown in bold print (gray background). Any read access to unimplemented addresses will return undefined data, while most write access will have no effect. However, a few locations are reserved and not user configurable in the 73S1210F ...
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... Serial Port 0, Reload Register, low byte Flash Control Flash Page Address Interrupt Enable Register 1 Interrupt Priority Register 1 Serial Port 0, Reload Register, high byte Serial Port 1, Reload Register, high byte Interrupt Request Control Register Timer 2 Control Program Status Word Keypad Column 73S1210F Data Sheet 19 ...
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... Data Sheet Name Location Reset Value KROW 0XD2 0x3F KSCAN 0XD3 0x00 KSTAT 0XD4 0x00 KSIZE 0XD5 0x00 KORDERL 0XD6 0x00 KORDERH 0XD7 0x00 BRCON 0xD8 0x00 A 0xE0 0x00 B 0xF0 0x00 1.5.3 External Data Special Function Registers (SFRs) A map of the XRAM Special Function Registers is shown in Table 8. The smart card registers are listed separately in Table 107 ...
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... RS1 RS OV Function RS1/RS0 Bank Selected 00 Bank 0 01 Bank 1 10 Bank 2 11 Bank 3 UDIR70 define individual pins as input or output Table 10: Port Registers Description 73S1210F Data Sheet LSB – P Location (0x00 – 0x07) (0x08 – 0x0F) (0x10 – 0x17) (0x18 – 0x1F) 21 ...
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... Oscillator and Clock Generation The 73S1210F has one oscillator circuit for the main CPU clock. The main oscillator circuit is designed to operate with various crystal or external clock frequencies. An internal divider working in conjunction with a PLL and VCO provides a 96MHz internal clock within the 73S1210F. 96 MHz is the recommended frequency for proper operation of specific peripheral blocks such as the specific timers, ISO 7816 UART and interfaces, Step-up converter, and keypad ...
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... MCLKCtl.1 MCT.1 MCLK = (MCount*2 + 4)* F MCLKCtl.0 MCT.0 that MCLK = (2*2 + 4)*12.00MHz = 96MHz. Rev. 1.4 = 96MHz XTAL F (MHz) Mcount (N) XTAL 12.00 2 9.60 3 8.00 4 6.86 5 6.00 6 Table 12: The MCLKCtl Register SCEN – – MCT.2 Function . The default value is MCount = 2h such XTAL 73S1210F Data Sheet LSB MCT.1 MCT.0 23 ...
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... Data Sheet MPU Clock Control Register (MPUCKCtl): 0xFFA1 0x0C MSB – – Bit Symbol MPUCKCtl.7 – MPUCKCtl.6 – MPUCKCtl.5 MDIV.5 This value determines the ratio of the MPU master clock frequency to the MPUCKCtl.4 MDIV.4 VCO frequency (MCLK) such that MPUCKCtl.3 MDIV ...
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... Debounce Circuit INT MPU PWRDN* *PWRDN bit in MISCtl0 Power Control Figure 5: Detailed Power Management Logic Block Diagram The 73S1210F contains a power supply and converter circuit that takes power from any one of three sources BUS BAT V is specified to range from 2.7 to 6.5 volts. It can typically be supplied by a single cell battery with a PC voltage range of 2 ...
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... When placed into the “OFF” state, the 73S1210F will consume minimum current from V and V will be unavailable (V out = 0V and When in “ON” mode, the 73S1210F will operate normally, with all the features described in this document available. V and V will be available ( Whenever V power is supplied, the circuit will be automatically in the “ ...
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... The 73S1210F contains circuitry to disable portions of the device and place it into a lower power standby mode or power down the 73S1210F into its “OFF” mode. The standby mode will stop the core, clock subsystem and the peripherals connected to it. This is accomplished by either shutting off the power or disabling the clock going to the block ...
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... INT0 and the program can resume. Figure 7 shows the detailed logic for waking up the 73S1210F from a power down state using these specific interrupt sources. Figure 8 shows the timing associated with the power down mode. ...
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... An external event (RTC, Keypad, Card event, USB) occurs. t4: PWRDN bit and PWRDN signal are cleared by external event. t5: High-speed oscillator/PLL/VCO operating. t6: After 512 MPU clock cycles, INT0 to MPU is asserted. t7: INT0 causes MPU to exit STOP condition. Rev. 1 Figure 8: Power Down Sequencing 73S1210F Data Sheet text ...
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... Data Sheet External Interrupt Control Register (INT5Ctl): 0xFF94 0x00 MSB PDMUX – Bit Symbol When set = 1, enables interrupts from Keypad (normally going to int5), Smart Card interrupts (normally going to int4), or USR(7:0) pins (int0) to cause interrupt on int0. The assertion of the interrupt to int0 is delayed by INT5Ctl ...
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... The HSOEN bit should never be set under normal circumstances. Power down control should only be initiated via use of the PWRDN bit in MISCtl0. Rev. 1.4 Table 16: The MISCtl1 Register FRPEN FLSH66 – Function Table 17: The MCLKCtl Register SCEN – – MCT.2 Function 73S1210F Data Sheet LSB – – – LSB MCT.1 MCT.0 31 ...
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... Data Sheet Power Control Register 0 (PCON): 0x87 0x00 The SMOD bit used for the baud rate generator is set up via this register. MSB SMOD – Bit Symbol PCON.7 SMOD If SM0D = 1, the baud rate is doubled. PCON.6 – PCON.5 – PCON.4 – ...
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... These are described in more detail in the respective sections. External interrupts are the interrupts external to the 80515 core, i.e. signals that originate in other parts of the 73S1210F, for example the USR I/O, smart card interface, analog comparators, etc. The external interrupt configuration is shown in Figure 9. USR0 ...
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... Data Sheet 1.7.5.1 Interrupt Overview When an interrupt occurs, the MPU will vector to the predetermined address as shown in the interrupt service has begun, it can only be interrupted by a higher priority interrupt. The interrupt service is terminated by a return from the RETI instruction. When a RETI is performed, the processor will return to the instruction that would have been next when the interrupt occurred ...
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... MSB – – Bit Symbol IEN2.0 ES1 ES1 = 0 – disable serial channel interrupt. Rev. 1.4 Table 20: The IEN1 Register EX6 EX5 EX4 EX3 Function Table 21: The IEN2 Register – – – – Function 73S1210F Data Sheet LSB EX2 – LSB – ES1 35 ...
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... Data Sheet Timer/Counter Control Register (TCON): 0x88 0x00 MSB TF1 TR1 Bit Symbol TCON.7 TF1 Timer 1 overflow flag. TCON.6 TR1 Not used for interrupt control. TCON.5 TF0 Timer 0 overflow flag. TCON.4 TR0 Not used for interrupt control. TCON.3 IE1 Interrupt 1 edge flag is set by hardware when the falling edge on external interrupt int1 is observed ...
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... Rev. 1.4 Table 24: The IRCON Register EX6 IEX5 IEX4 IEX3 Function Table 25: External MPU Interrupts Connection Polarity see USRIntCtlx see USRIntCtlx Edge selectable Edge selectable 73S1210F Data Sheet LSB IEX2 – Flag Reset Automatic Automatic Automatic Automatic N/A Automatic N/A Automatic N/A Automatic 37 ...
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... Enable external interrupt 5 EX6 Enable external interrupt 6 1.7.5.4 Power Down Interrupt Logic The 73S1210F contains special interrupt logic to allow INT0 to wake up the CPU from a power down (CPU STOP) state. See the Power Control Modes 1.7.5.5 Interrupt Priority Level Structure All interrupt sources are combined in groups, as shown in Table 27. ...
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... Chip Reset External interrupt 0 Timer 0 interrupt External interrupt 1 Timer 1 interrupt Serial channel 0 interrupt Serial channel 1 interrupt External interrupt 2 External interrupt 3 External interrupt 4 External interrupt 5 External interrupt 6 73S1210F Data Sheet LSB IP1.1 IP1.0 Interrupt Vector Address 0x0000 0x0003 0x000B 0x0013 0x001B 0x0023 0x0083 ...
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... UART The 80515 core of the 73S1210F includes two separate UARTs that can be programmed to communicate with a host. The 73S1210F can only connect one UART at a time since there is only one set of TX and Rx pins. The MISCtl0 register is used to select which UART is connected to the TX and RX pins. Each UART has a different set of operating modes that the user can select according to their needs ...
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... Sets CPU to Stop mode. Sets CPU to Idle mode. Table 36: The BRCON Register – – – – Function If BSEL = 0, the baud rate is derived using timer 1. If BSEL = 1 the baud rate generator circuit is used. . 73S1210F Data Sheet LSB STOP IDLE LSB – – 41 ...
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... RB80 in Special Function Register S0CON. 42 Table 37: The MISCtl0 Register – – – – Function This bit places the 73S1210F into a power down state UART loop back testing mode. The pins TXD and RXD are to be connected together externally (with SLPBK =1) and therefore: SLPBK SSEL Mode 0 0 ...
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... Receive interrupt flag, set by hardware after completion of a serial reception. Must be cleared by software. Rev. 1.4 Table 38: The S0CON Register SM20 REN0 TB80 RB80 Function Mode Description SM0 0 N 8-bit UART 0 2 9-bit UART 1 3 9-bit UART 1 73S1210F Data Sheet LSB TI0 RI0 SM1 ...
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... Data Sheet 1.7.6.2 Serial Interface 1 The Serial Interface 1 can operate in 2 modes: • Mode A This mode is similar to Mode 2 and 3 of Serial interface 0, 11 bits are transmitted or received: a start bit (0), 8 data bits (LSB first), a programmable 9th bit, and a stop bit (1). The 9th bit can be used to control the parity of the serial interface: at transmission, bit TB81 in receive, the 9th bit affects RB81 in Special Function Register S1CON ...
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... Function 13-bit Counter/Timer. 16-bit Counter/Timer. 8-bit auto-reload Counter/Timer. If Timer 1 M1 and M0 bits are set to '1', Timer 1 stops. If Timer 0 M1 and M0 bits are set to '1', Timer 0 acts as two independent 8-bit Timer/Counters. 73S1210F Data Sheet User (USR) LSB M1 M0 Timer 0 45 ...
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... Data Sheet Mode 0 Putting either timer/counter into mode 0 configures 8-bit timer/counter with a divide-by-32 prescaler. In this mode, the timer register is configured as a 13-bit register. As the count rolls over from all 1’s to all 0’s, it sets the timer overflow flag TF0. The overflow flag TF0 then can be used to request an interrupt ...
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... ET1 = 0 – disable timer 1 overflow interrupt. IEN0.2 EX1 EX1 = 0 – disable external interrupt 1. IEN0.1 ET0 ET0 = 0 – disable timer 0 overflow interrupt. IEN0.0 EX0 EX0 = 0 – disable external interrupt 0. Rev. 1.4 Table 43: The IEN0 Register ET2 ES0 ET1 EX1 Function 73S1210F Data Sheet LSB ET0 EX0 47 ...
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... Data Sheet Interrupt Enable 1 Register (IEN1): 0xB8 0x00 MSB – SWDT Bit Symbol IEN1.7 – IEN1.6 SWDT Watchdog timer start/refresh flag. Set to activate/refresh the watchdog timer. When directly set after setting WDT, a watchdog timer refresh is performed. Bit SWDT is reset by the hardware 12 clock cycles after it has been set. ...
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... DS_1210F_001 1.7.9 User (USR) Ports The 73S1210F includes 8 pins of general purpose digital I/O (GPIO). On reset or power-up, all USR pins are inputs until they are configured for the desired direction. The pins are configured and controlled by the USR70 and UDIR70 SFRs. Each pin declared as USR can be configured independently as an input ...
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... Data Sheet External Interrupt Control Register (USRIntCtl1) : 0xFF90 0x00 MSB – U1IS.6 External Interrupt Control Register (USRIntCtl2) : 0xFF91 0x00 MSB – U3IS.6 External Interrupt Control Register (USRIntCtl3) : 0xFF92 0x00 MSB – U5IS.6 External Interrupt Control Register (USRIntCtl4) : 0xFF93 0x00 MSB – ...
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... DS_1210F_001 1.7.10 Analog Voltage Comparator The 73S1210F includes a programmable comparator that is connected to the ANA_IN pin. The comparator can be configured to trigger an interrupt if the input voltage rises above or falls below a selectable threshold voltage. The comparator control register should not be modified when the analog interrupt (ANAIEN bit in the INT6Ctl generated when modifying the threshold ...
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... Data Sheet External Interrupt Control Register (INT6Ctl): 0xFF95 0x00 MSB – – Bit Symbol INT6Ctl.7 – INT6Ctl.6 – INT6Ctl.5 VFTIEN VDD fault interrupt enable. INT6Ctl.4 VFTINT VDD fault interrupt flag. 2 INT6Ctl.3 I2CIEN I C interrupt enabled. 2 INT6Ctl.2 I2CINT I C interrupt flag. ...
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... DS_1210F_001 1.7.11 LED Driver The 73S1210F provides a single dedicated output pin for driving an LED. The LED driver pin can be configured as a current source that will pull to ground to drive an LED that is connected to VDD without the need for an external current limiting resistor. This pin may be used as general purpose output with the programmed pull-down current and a strong (CMOS) pull-up, if enabled ...
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... Data Sheet 2 1.7. Master Interface The 73S1210F includes a dedicated fast mode, 400kHz I or write bytes of data per data transfer frame. The MPU communicates with the interface through six dedicated SFR registers: • Device Address (DAR) • Write Data (WDR) • ...
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... MSB LSB 1 10-17 ACK bit ACK bit 2 Figure 10 Write Mode Operation IEN1 and IRCON registers for masking and flag operation. 73S1210F Data Sheet 18 STOP condition Secondary Write Data [7:0] MSB LSB 18 19-26 27 ACK bit STOP condition 2 C Master Bus. Also write 2 C Slave device ...
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... Data Sheet Figure 11 shows the timing of the I Transfer length (CSR bit0) Start I2C (CSR bit1) I2c_Interrupt SDA Device Address MSB SCL START condition Transfer length (CSR bit0) Start I2C (CSR bit1) I2c_Interrupt SDA Device Address MSB SCL START condition read mode: ...
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... WDR.7 WDR.6 WDR.5 WDR.4 Data to be written to the I WDR.3 WDR.2 WDR.1 WDR.0 Rev. 1.4 Table 57: The DAR Register DVADR.3 DVADR.2 DVADR.1 Function Table 58: The WDR Register WDR.4 WDR.3 WDR.2 Function 2 C slave device. 73S1210F Data Sheet LSB DVADR.0 I2CRW LSB WDR.1 WDR.0 57 ...
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... Data Sheet I2C Secondary Write Data Register (SWDR): 0XFF82 0x00 MSB SWDR.7 SWDR.6 SWDR.5 Bit SWDR.7 SWDR.6 SWDR.5 SWDR.4 Second Data byte to be written to the I Control and Status register (CSR) is set = 1. SWDR.3 SWDR.2 SWDR.1 SWDR.0 I2C Read Data Register (RDR): 0XFF83 0x00 MSB RDR ...
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... Table 61: The SRDR Register SRDR.4 SRDR.3 SRDR.2 Function 2 C slave device if bit 0 (I2CLEN) of the Control Table 62: The CSR Register – – – AKERR Function 2 C transaction. Automatically reset to 0 when the bus 73S1210F Data Sheet LSB SRDR.1 SRDR.0 LSB I2CST I2CLEN 59 ...
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... Data Sheet External Interrupt Control Register (INT6Ctl): 0xFF95 0x00 MSB – – Bit Symbol INT6Ctl.7 – INT6Ctl.6 – INT6Ctl.5 VFTIEN VDD fault interrupt enable. INT6Ctl.4 VFTINT VDD fault interrupt flag. INT6Ctl.3 I2CIEN When set = 1, the I When set = 1, the I INT6Ctl.2 ...
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... DS_1210F_001 1.7.13 Keypad Interface The 73S1210F supports a 30-button (6 rows x 5 columns) keypad (SPST Mechanical Contact Switches) interface using 11 dedicated I/O pins. Figure 12 shows a simplified block diagram of the keypad interface. Keypad Clock Column Value (1) KCOL Register Keypad Clock Row Value ...
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... Data Sheet written into the KCOL and KROW 12MHz crystal. The clock is enabled by setting bit 6 – KBEN – in the and Clock Generation section) to carry out scanning and debouncing. The keypad size can be adjusted within the KSIZE register. Normal scanning is performed by hardware when the SCNEN bit is set the 13 shows the flowchart of how the hardware scanning operates ...
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... Is (are) the key(s) Yes released ? (*) No KSCAN Register: Debouncing Time (*) Key release is cheked by looking for a low level on any row. 73S1210F Data Sheet KSTAT Register: Enable HW Scanning Enable Keypad Interrupt KSCAN Register: Debouncing Time KSIZE Register: Keypad Size Definition KSCAN Register: Scanning Rate ...
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... Data Sheet Keypad Column Register (KCOL): 0xD1 0x1F This register contains the value of the column of a key detected as valid by the hardware. In bypass mode, this register firmware writes directly this register to carry out manual scanning. MSB – – Bit Symbol KCOL.7 – ...
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... KSTAT.0 KYDTEN when cleared the KEYDET cannot cause an interrupt. KEYDET can still get set even if the interrupt is not enabled. Rev. 1.4 Table 66: The KSCAN Register Function Table 67: The KSTAT Register – – KEYCLK HWSCEN KEYDET Function 73S1210F Data Sheet LSB LSB KYDTEN 65 ...
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... Data Sheet Keypad Scan Time Register (KSIZE): 0xD5 0x00 This register is not applicable when HWSCEN is not set. Unused row inputs should be connected to VDD. MSB – – ROWSIZ.2 ROWSIZ.1 ROWSIZ.0 COLSIZ.2 COLSIZ.1 COLSIZ.0 Bit Symbol KSIZE.7 – KSIZE.6 – KSIZE.5 ROWSIZ ...
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... Column to scan 3 Rev. 1.4 registers, Column Scan Order(14:0) is grouped into 5 sets of 3 bits Table 69: The KORDERL Register 2COL.1 2COL.0 1COL.2 Function rd (lsb’s Table 70: The KORDERH Register 5COL.0 4COL.2 4COL.1 Function (msb). 73S1210F Data Sheet LSB 1COL.1 1COL.0 LSB 4COL.0 3COL.2 67 ...
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... Data Sheet External Interrupt Control Register (INT5Ctl): 0xFF94 0x00 MSB PDMUX – Bit Symbol INT5Ctl.7 PDMUX Power down multiplexer control. INT5Ctl.6 – INT5Ctl.5 – INT5Ctl.4 – INT5Ctl.3 – INT5Ctl.2 – INT5Ctl.1 KPIEN Enables Keypad interrupt when set = 1. This bit indicates the Keypad logic has set Key_Detect bit and a key INT5Ctl ...
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... DS_1210F_001 1.7.15 Smart Card Interface Function The 73S1210F integrates one ISO-7816 (T=0, T=1) UART, one complete ICC electrical interface as well as an external smart card interface to allow multiple smart cards to be connected using the Teridian 8010 family of interface devices. Figure 14 shows the simplified block diagram of the card circuitry (UART + interfaces), with detail of dedicated XRAM registers ...
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... USR GPIO pins. The external 73S8010x devices directly connect the I/O (SIO) and clock (SCLK) signals and control 2 is handled via the I C interface. Figure 15 shows how multiple 8010 devices can be connected to the 73S1210F. VPC PRES PRES VCC ...
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... ISO 7816 UART An embedded ISO 7816 (hardware) UART is provided to control communications between a smart card and the 73S1210F MPU. The UART can be shared between the one built-in ICC interface and the external ICC interface. Selection of the desired interface is made by register SCSel. Control of the ...
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... ATR response response is not provided within the pre-programmed timeout period, an interrupt is generated and the firmware can then take appropriate action, including instructing the 73S1210F to begin a deactivation sequence. Once commanded, the deactivation sequencer goes through the power down sequence as defined in the ISO 7816-3 specification ATR response is received, the hardware looks for a TS byte that determines direct/inverse convention ...
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... UART to communicate with the internal smart card. Rev. 1 Figure 17: Deactivation Sequence FDReg to adjust the ETU and CLK. The firmware may also SCCLK (SCECLK Figure 18 shows the ETU and CLK control circuits. The 73S1210F Data Sheet for external interface). 73 ...
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... Extra Guard Time register (EGT), and between the last byte received by the 73S1210F and the first byte transmitted by the 73S1210F using the Block Guard Time register (BGT). Other than the protocol checks described above, the firmware is responsible for all protocol checking and error recovery ...
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... Synchronous Operation Mode The 73S1210F supports synchronous operation. When sync mode is selected for either interface, the CLK signal is generated by the ETU counter. The values in c, SCCLK, and obtain the desired sync CLK rate. There is only one ETU counter and therefore, in sync mode, the interface must be selected to obtain a smart card clock signal ...
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... Data Sheet Special Notes Regarding Synchronous Mode Operation When the SCISYN or SCESNC bits (SPrtcol, bit 7, bit 5, respectively) are set, the selected smart card interface operates in synchronous mode and there are changes in the definition and behavior of pertinent register bits and associated circuitry. The following requirements are to be noted: 1 ...
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... Note that in Sync mode input is sampled on the rising edge of CLK. IO changes on the falling edge of CLK, either from the card or from the 73S1210F. The RST signal to the card is directly controlled by the RSTCRD bit (non-inverted) via the MPU and is shown as an example of a possible RST pattern. ...
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... Data Sheet CLK Data from Card -end of ATR IO RLength Count - was set for length of ATR RLength Interrupt CLK Stop CLK Stop Level IO Bit IODir Bit TX/RX Mode Bit TX = '1' 1. Interrupt generated when Rlength counter is MAX. 2. Read and clear Interrupt. 3. Set CLK Stop and CLK Stop level high in Interrupt routine. ...
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... Read and clear Interrupt Receive data in 9 bit mode RLength Count MAX Rlen=9 Stop CLK after receiving the last byte and protection bit. 73S1210F Data Sheet Data from Card (Bit 1) Rlen =1 RX FIFO Protection Bit is ready for CPU read 3._ Reload RLength counter 2 ...
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... Data Sheet 1.7.15.6 Smart Card SFRs Smart Card Select Register (SCSel): 0xFE00 0x00 The Smart Card Select register is used to determine which smart card interface is using the ISO UART. The internal Smart Card has integrated 7816-3 compliant sequencer circuitry to drive an external smart card interface ...
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... Table 73: The SCInt Register RXDAV TXEVT TXSENT Function SFR. This bit is cleared when the STXCtl SFR. Additional information can be found in that register SRXCtl register is read. 73S1210F Data Sheet LSB TXERR RXERR CRDCtl register to determine STXCtl register is read. STXCtl register is read. SRXCtl register ...
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... Data Sheet Smart Card Interrupt Enable Register (SCIE): 0xFE02 0x00 When set to 1, the respective condition can cause a smart card interrupt. When set the respective condition cannot cause an interrupt. When disabled, the respective bit in the Smart Card Interrupt register can still be set, but it will not interrupt the MPU ...
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... If not set, the deactivation sequence shall start when the VCCTMR times out. VccCtl.3 VCCOK (Read only). Indicates that V VccCtl.2 – VccCtl.1 – This bit controls the power-off mode of the 73S1210F circuit power off normal operation. When in power down mode, VccCtl.0 SCPWRDN application has no effect until V Rev ...
Page 84
... Data Sheet Stable Timer Register (VccTmr): 0xFE04 0x0F programmable timer is provided to set the time from activation start (setting the VCCSEL.1 and VCCSEL.0 bits to non-zero) to when VCC_OK is evaluated. VCC_OK must be true at the end of this timers programmed interval (tto in is not true and the end of the interval (tto), the Card Event interrupt will be set, and a deactivation sequence shall begin including clearing of the VCCSEL bits ...
Page 85
... Enable pull-down current on DETCARD pin. Card Inserted - (Read only card inserted card not inserted. A change in the value of this bit is a “card event.” A read of this bit indicates whether smart card is inserted or not inserted in conjunction with the DETPOL setting. 73S1210F Data Sheet LSB PDEN CARDIN 85 ...
Page 86
... Data Sheet TX Control/Status Register (STXCtl): 0xFE06 0x00 This register is used to control transmission of data to the smart card. Some control and some status bits are in this register. MSB I2CMODE – TXFULL Bit Symbol I2C Mode - When in sync mode and this bit is set, and when the RLen count value = max or 0, the source of the smart card data for IO pin (or SIO pin) will STXCtl ...
Page 87
... Parity Error - (Read only The logic detected a parity error on incoming SRXCtl.0 PARITYE data from the smart card. Cleared when read. Will generate an RXERR interrupt. Rev. 1.4 Table 79: The STXData Register STXDAT.2 Function Table 80: The SRXCtl Register CRCERR RXFULL RXEMTY RXOVRR PARITYE Function 73S1210F Data Sheet LSB STXDAT.1 STXDAT.0 LSB 87 ...
Page 88
... Data Sheet SRX Data Register (SRXData): 0xFE09 0x00 MSB SRXDAT.7 SRXDAT.6 SRXDAT.5 SRXDAT.4 SRXDAT.3 SRXDAT.2 SRXDAT.1 SRXDAT.0 Bit SRXData.7 SRXData.6 SRXData.5 SRXData.4 (Read only) Data received from the smart card. Data received from the smart card gets stored in a FIFO that is read by the firmware. ...
Page 89
... CLK is enabled CLK is not enabled. When asserted, the CLK will SCCtl.0 CLKOFF stop at the level selected by CLKLVL. This bit has no effect if in bypass mode. Rev. 1.4 Table 82: The SCCtl Register IO IOD C8 Function RLength SPrtcol register) the sense of this bit is non-inverted, if 73S1210F Data Sheet LSB C4 CLKLVL CLKOFF register description. This bit is RLength 89 ...
Page 90
... Data Sheet External Smart Card Control Register (SCECtl): 0xFE0B 0x00 This register is used to directly set and sample signals of External Smart Card interface. There are three modes of asynchronous operation, an “automatic sequence” mode, and bypass mode. Clock stop per the ISO 7816-3 interface is also supported but firmware must handle the protocol for SIO and SCLK for ...
Page 91
... SCDIR.6 – SCDIR.5 – SCDIR.4 – SCDIR.3 C8D SCDIR.2 C4D SCDIR.1 – SCDIR.0 – Rev. 1.4 Table 84: The SCDIR Register – – C8D Function 1 = input output. Smart Card C8 direction input output. Smart Card C4 direction. 73S1210F Data Sheet LSB C4D – – 91 ...
Page 92
... Data Sheet Protocol Mode Register (SPrtcol): 0xFE0D 0x03 This register determines the protocol to be use when communicating with the selected smart card. This register should be updated as required when switching between smart card interfaces. MSB SCISYN MOD9/8B SCESYN Bit Symbol Smart Card Internal Synchronous mode - Configures internal smart card interface for synchronous mode ...
Page 93
... A SCECLK.1 ECLKFS.1 register value = 0 will default to the same effect as register value = 1. SCECLK.0 ECLKFS.0 Rev. 1.4 Table 86: The SCCLK Register Function Table 87: The SCECLK Register ECLKFS.4 ECLKFS.3 ECLKFS.2 Function 73S1210F Data Sheet LSB LSB ECLKFS.1 ECLKFS.0 93 ...
Page 94
... Data Sheet Parity Control Register (SParCtl): 0xFE11 0x00 This register provides the ability to configure the parity circuitry on the smart card interface. The settings apply to both integrated smart card interfaces. MSB – DISPAR BRKGEN BRKDET RETRAN DISCRX Bit Symbol SParCtl.7 – ...
Page 95
... SByteCtl.4 BRKDUR.1 Break Duration Select – ETU 1.5 ETU ETU reserved. Determines the length of a Break signal which is generated SByteCtl.3 BRKDUR.0 when detecting a parity error on a character reception in T=0 mode. SByteCtl.2 – SByteCtl.1 – SByteCtl.0 – Rev. 1.4 Table 89: The SByteCtl Register BRKDUR.1 BRKDUR.0 Function 73S1210F Data Sheet LSB – – – 95 ...
Page 96
... Data Sheet FD Control Register (FDReg): 0xFE13 0x11 This register uses the transmission factors F and D to set the ETU (baud) rate. The values in this register are mapped to the ISO 7816 conversion factors as described below. The CLK signal for each interface is created by dividing a high-frequency, intermediate signal (MSCLK ...
Page 97
... Data Sheet 0100 0101 1116 1488 2232 2976 1116 1488 558 744 279 372 186 248 140 186 112 149 70 93 1100 1101 ...
Page 98
... Data Sheet CRC MS Value Registers (CRCMsB): 0xFE14 0xFF, (CRCLsB): 0xFE15 0xFF MSB CRC.15 CRC.14 MSB CRC.7 CRC.6 The 16-bit CRC value forms the TX CRC word in TX mode (write value) and the RX CRC in RX mode (read value). The initial value of CRC to be used when generating a CRC to be transmitted at the end of a message (after the last TX byte is sent) when enabled in T=1 mode ...
Page 99
... Most-significant bit for 9-bit EGT timer. See the Time in ETUs between the start bit of the last received character to start bit of the first character transmitted to the smart card. Default value is 22. Table 96: The EGT Register EGT.4 EGT.3 Function 73S1210F Data Sheet LSB BGT.1 BGT.2 BGT.0 EGT register. LSB EGT ...
Page 100
... These registers are used to set the Block Waiting Time(27:0) (BWT). All of these parameters define the maximum time the 73S1210F will have to wait for a character from the smart card. These registers serve a dual purpose. When T=1, these registers are used to set up the block wait time. The block wait time defines the time in ETUs between the beginning of the last character sent to smart card and the start bit of the first character received from smart card ...
Page 101
... ATRTO.3 Table 104: The ATRMsB Register ATRTO.12 ATRTO.11 Table 105: The STSTO Register TST0.4 TST0.3 TST0.1 Table 106: The RLength Register RLen.5 RLen.4 RLen.3 73S1210F Data Sheet LSB ATRTO.1 ATRTO.2 ATRTO.0 LSB ATRTO.10 ATRTO.9 ATRTO.8 LSB TST0.2 TST0.0 LSB RLen.1 RLen.2 RLen ...
Page 102
... Data Sheet Shaded locations indicate functions that are not provided in the synchronous mode. Name Address b7 SCSel FE00 SCInt FE01 WAITTO/ RLIEN SCIE FE02 WTOI/ RLIEN VccCtl FE03 VCCSEL.1 VCCSEL.0 VCCTmr FE04 CRDCtl FE05 DEBOUN STXCtl FE06 I2CMODE STXData FE07 SRXCtl ...
Page 103
... Note: The V Fault factory default can be set to any threshold as defined by bits VDDFTH(2:0). The DD 73S1210F has the capability to burn fuses at the factory to set the factory default to any of these voltages. Contact Teridian for further details. Rev. 1.4 falls below the V DD Table 108: The VDDFCtl Register – ...
Page 104
... SW_MOM VDD C12 C13 C14 0.1uF 0.1uF 0.1uF R8 100 RV1 2 D2 C15 C19 + 10K 5.0V Zener 1uF 0.1uF LCD BRIGHTNESS ADJUST Figure 25: 73S1210F Typical Application Schematic C2 22pF VDD 10uF 0.1uF Input Power Supply (2.7 - 6.5V) C5 0.1uF 10k C6 10uF 10uH ...
Page 105
... Unless otherwise noted all specifications are valid over these temperatures and supply voltage ranges: Parameter Supply Voltage V PC Supply Voltage V BUS Supply Voltage V BAT Ambient Operating Temperature (Ta) Rev. 1.4 73S1210F Data Sheet , ground, and each other. CC Rating -0.5 to 4.0 VDC -0.5 to 6.6 VDC -0.5 to 6.6 VDC -0.5 to 6.6 VDC -60 to 150°C -0 ...
Page 106
... Data Sheet 3.3 Digital IO Characteristics These requirements pertain to digital I/O pin types with consideration of the specific pin function and configuration. The LED(1:0) pins have pull-ups that may be enabled. The Row pins have 100kΩ pull- ups. Symbol Parameter Voh Output level, high ...
Page 107
... Crystal resonant frequency 3.5 DC Characteristics: Analog Input Symbol Parameter V Voltage Threshold THTOL Tolerance Rev. 1.4 Condition Min -0.3 0.7*VDD GND < Vin < Vdd -10 Fundamental mode 6 Condition Min Selected Threshold -3% Value 73S1210F Data Sheet Typ. Max Unit 1.5 0.3*VDD V 1.6 Vdd+.0.3 V μ MHz Typ. Max Unit +3% V 107 ...
Page 108
... Data Sheet 3.6 Smart Card Interface Requirements Symbol Parameter Card Power Supply (V ) Regulator CC General conditions, -40°C < T < 85°C, 4.75V < V Card supply Voltage V including ripple and CC noise V V Ripple CCrip CC Card supply output I CCmax current I I fault current CCF CC Isc ...
Page 109
... 1mA 35pF for CLK, L 10 200pF for RST, L 10 35pF CLK ≤ 45 20MHz, CLKIN duty cycle is 48% to 52%. 73S1210F Data Sheet Typ. Max Unit +0. 0 ...
Page 110
... Data Sheet 3.7 DC Characteristics Symbol Parameter Supply Current @ and V unconnected) BUS BAT Supply Current @ and V unconnected) BUS BAT I PC Supply Current @ and V unconnected) BUS BAT Supply Current @ V VBUS Supply Current @ V VBUS I VBUS Supply Current @ V VBUS Supply Current @ V VBAT ...
Page 111
... CPU clock @ 3.69MHz Power down (-40° to 85°C) Power down (25°C) Circuit ON V off DDINTERNAL BUS 20µA or BAT Circuit OFF should be ceramic VCC with low ESR CC (<100MΩ). pin. DD Condition V = 1.8V CC 73S1210F Data Sheet 29 33 15.5 18 13.5 15 < 0.2 0.4 0.01 1 3.5 50 8.0 10.0 12.0 2.0 4.7 10.0 0.2 1.0 ...
Page 112
... Data Sheet 4 Equivalent Circuits X12LIN ESD ENABLE ENABLEb X32LIN ESD 112 VDD Figure 26: 12 MHz Oscillator Circuit VDD >1MEG Figure 27: 32KHz Oscillator Circuit DS_1210F_001 X12OUT ESD To circuit X32OUT ESD To circuit Rev. 1.4 ...
Page 113
... DS_1210F_001 Output Disable Data From circuit To circuit Output Disable Data From circuit Rev. 1.4 VDD STRONG PFET STRONG NFET Figure 28: Digital I/O Circuit VDD STRONG PFET STRONG NFET Figure 29: Digital Output Circuit 73S1210F Data Sheet PIN ESD PIN ESD 113 ...
Page 114
... Data Sheet Pull-up Disable Output Disable Data From circuit To circuit Figure 30: Digital I/O with Pull Up Circuit Output Disable Data From circuit To circuit Pull-down Enable Figure 31: Digital I/O with Pull Down Circuit 114 DS_1210F_001 VDD VERY WEAK PFET STRONG PFET PIN ESD STRONG ...
Page 115
... To circuit Rev. 1.4 ESD Figure 32: Digital Input Circuit STRONG PFET STRONG NFET Figure 33: OFF_REQ Interface Circuit STRONG PFET STRONG NFET Figure 34: Keypad Row Circuit 73S1210F Data Sheet PIN VDD VERY WEAK PFET ESD PIN ESD VERY WEAK NFET VDD 100k OHM PIN ...
Page 116
... Data Sheet Output Disable Data From circuit To circuit Pullup Disable Data From circuit To circuit Current Value Control 116 VDD 1200 OHMS MEDIUM PFET STRONG NFET Figure 35: Keypad Column Circuit VDD STRONG STRONG Figure 36: LED Circuit DS_1210F_001 PIN ESD PFET PIN ...
Page 117
... From circuit Rev. 1.4 This buffer has a special input Vih>0.7*VDD ESD R= 20kΩ To Comparator Input PIN ESD Figure 38: Analog Input Circuit VCC Figure 39: Smart Card Output Circuit 73S1210F Data Sheet threshold: To Circuit Logic STRONG ESD PFET PIN ESD STRONG NFET 117 ...
Page 118
... Data Sheet DELAY From circuit To circuit To circuit Pull-down Enable Pull-up Disable To circuit Pull-down Enable 118 STRONG PFET 125ns STRONG NFET Figure 40: Smart Card I/O Circuit VERY WEAK NFET Figure 41: PRES Input Circuit VERY WEAK PFET Figure 42: PRESB Input Circuit DS_1210F_001 VCC ...
Page 119
... DS_1210F_001 PIN Rev. 1.4 VPC R= 24kΩ ESD Figure 43: ON_OFF Input Circuit 73S1210F Data Sheet To Circuit Logic 119 ...
Page 120
... ROW2 24 TERIDIAN GND 25 N/C 26 73S1210F N/C 27 VDD 28 USR5 29 USR4 30 USR3 31 USR2 32 ROW3 33 USR1 34 120 CAUTION: Use handling procedures necessary for a static sensitive component Figure 44: 73S1210F 68 QFN Pinout DS_1210F_001 VDD 68 GND 67 66 LIN 65 VPC VBAT 64 ON_OFF 63 VBUS AUX1 60 AUX2 59 VCC 58 RST 57 GND ...
Page 121
... USR7 13 USR6 14 GND 15 VDD 16 USR5 17 USR4 18 USR3 19 USR2 20 USR1 21 USR0 22 Rev. 1.4 CAUTION: Use handling procedures necessary for a static sensitive component. TERIDIAN 73S1210F Figure 45: 73S1210F 44 QFN Pinout 73S1210F Data Sheet VPC 44 ON_OFF AUX1 41 AUX2 40 VCC 39 RST 38 GND 37 CLK PRES 34 121 ...
Page 122
... QFN Package Outline Notes: 6.3mm x 6.3mm exposed pad area must remain UNCONNECTED (clear of PCB traces or vias). Controlling dimensions are in mm. 8.00 7. TOP VIEW 8.00 0.42 0.24/0.60 6.30 6.15/6.45 0.45 0.42 0.24/0.60 6.30 6.15/6.45 6.40 BOTTOM VIEW Figure 46: 73S1210F 68 QFN Mechanical Drawing 122 7.75 8.00 12° PIN#1 ID R0. 0.20 2 0.15/0.25 3 6.40 8.00 0.40 FOR ODD TERMINAL/SIDE DS_1210F_001 0.65 0.85 0.2 0.00/0.05 ...
Page 123
... QFN Package Outline Notes: 5.1mm x 5.1mm exposed pad area must remain UNCONNECTED (clear of PCB traces or vias). Controlling dimensions are in mm. 7.00 6. TOP VIEW 7.00 0.42 0.24/0.60 5.10 4.95/5.25 0.45 0.42 0.24/0.60 5.10 4.95/5.25 5.00 BOTTOM VIEW Figure 47: 73S1210F 44 QFN Package Drawing Rev. 1.4 6.75 7.00 12° PIN#1 ID R0. 0.23 2 0.18/0.30 3 5.00 7.00 0.50 FOR ODD TERMINAL/SIDE 73S1210F Data Sheet 0.65 0.85 0.2 0.00/0.05 ...
Page 124
... Evaluation Board User’s Guide 73S12xxF Software User’s Guide 73S12xxF Synchronous Card Design Application Note 9 Contact Information For more information about Teridian Semiconductor products or to check the availability of the 73S1210F, contact us at: 6440 Oak Canyon Road Suite 100 Irvine, CA 92618-5201 ...
Page 125
... PGADDR. 8, changed the reset value for RTCCtl from “0x81” to “0x00”. 7, removed the Mcount 7 row. through Table 53, changed the names of registers USRIntCtl0 1.7.9, added a note about USR pins defaulting as inputs after ATRMsB 73S1210F Data Sheet from FE21 to FE1F. 125 ...
Page 126
... Data Sheet In Section the activation sequence begins (either by VCCOK=1 or VCCTMR timeout) and will go high ½ the ETU period thereafter.” In Section into three primary types. These are commonly referred to as 2-wire, 3-wire and I2C synchronous cards. Each card type requires different control and timing and therefore requires different algorithms to access ...