71M6541F Maxim, 71M6541F Datasheet - Page 72

• Manufacturer Part Number: 71M6541F
• Description: The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are Teridian™ 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core, low-power RTC with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

DIO pin that is connected to CS. Multiple 8-bit or less commands such as those shown in
through
When the transaction is finished, CS must be lowered. At the end of a Read transaction, the EEPROM is
driving SDATA, but transitions to Hi-Z (high impedance) when CS falls. The firmware should then
71M6541D/F/G and 71M6542F/G Data Sheet
The timing diagrams in
commands begin when the EECTRL (SFR 0x9F) register is written. Transactions start by first raising the
immediately issue a write command with CNT=0 and HiZ=0 to take control of SDATA and force it to a
low-Z state.
72
3:0
4
SDATA output Z
Figure 26
SDATA output Z
SDATA (input)
SDATA (output)
EECTRL Byte Written
SCLK (output)
SDATA output Z
SDATA (output)
EECTRL Byte Written
SCLK (output)
EECTRL Byte Written
SCLK (output)
Write -- With HiZ
CNT[3:0]
Write -- No HiZ
BUSY (bit)
BUSY (bit)
BUSY (bit)
READ
RD
are then sent via EECTRL and EEDATA.
Figure 22
Figure 22: 3-wire Interface. Write Command, HiZ=0.
W
W
Figure 23: 3-wire Interface. Write Command, HiZ=1
Figure 24: 3-wire Interface. Read Command.
Indicates that EEDATA (SFR 0x9E) is to be filled with data from EEPROM.
Specifies the number of clocks to be issued. Allowed values are 0
through 8. If RD=1, CNT bits of data are read MSB first, and right
justified into the low order bits of EEDATA. If RD=0, CNT bits are sent
MSB first to the EEPROM, shifted out of the MSB of EEDATA. If
CNT[3:0] is zero, SDATA simply obeys the HiZ bit.
through
D7
D7
D7
Figure 26
D6
D6
D6
CNT Cycles (8 shown)
CNT Cycles (6 shown)
CNT Cycles (6 shown)
(HiZ)
(LoZ)
D5
(LoZ)
D5
describe the 3-wire EEPROM interface behavior. All
D5
D4
D4
D4
D3
D3
D3
D2
D2
D2
INT5
INT5
(HiZ)
D1
Figure 22
D0
INT5
Rev 2