71M6541F Maxim, 71M6541F Datasheet - Page 119

• Manufacturer Part Number: 71M6541F
• Description: The 71M6541D/71M6541F/71M6541G/71M6542F/71M6542G are Teridian™ 4th-generation single-phase metering SoCs with a 5MHz 8051-compatible MPU core, low-power RTC with digital temperature compensation, flash memory, and LCD driver
• Manufacturer: Maxim

Rev 2
Name
MUX_DIV[3:0]
OPT_BB
OPT_FDC[1:0]
OPT_RXDIS
OPT_RXINV
OPT_TXE [1:0]
OPT_TXINV
OPT_TXMOD
OSC_COMP
PB_STATE
PERR_RD
PERR_WR
PLL_OK
SFR FC[6]
SFR FC[5]
SFR F8[0]
SFR F9[4]
Location
2100[7:4]
2457[5:4]
2456[3:2]
28A0[5]
2457[0]
2457[2]
2457[1]
2456[0]
2456[1]
Rst Wk Dir
00 –
0
0
0
0
0
0
0
0
0
0
0
0
–
–
–
–
–
–
–
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W Invert OPT_TX when 1. This inversion occurs before modulation.
R/W
R/W
R/W
R
R
Description
MUX_DIV[3:0] is the number of ADC time slots in each MUX frame. The
maximum number of time slots is 11.
Configures the input of the optical port to be a DIO pin to allow it to be
bit-banged. In this case, DIO5 becomes a third high speed UART. Refer to
2.5.7 UART and Optical Interface
(Third UART)” sub-heading on
Selects OPT_TX modulation duty cycle.
OPT_RX can be configured as an input to the optical UART or as SEGDIO55.
OPT_RXDIS = 0 and LCD_MAP[55] = 0: OPT_RX
OPT_RXDIS = 1 and LCD_MAP[55] = 0: DIO55
OPT_RXDIS = 0 and LCD_MAP[55] = 1: SEG55
OPT_RXDIS = 1 and LCD_MAP[55] = 1: SEG55
Inverts result from OPT_RX comparator when 1. Affects only the UART input.
Has no effect when OPT_RX is used as a DIO input.
Configures the OPT_TX output pin.
If LCD_MAP[51] = 0:
If LCD_MAP[51] = 1:
Enables modulation of OPT_TX. When OPT_TXMOD is set, OPT_TX is
modulated when it would otherwise have been zero. The modulation is applied
after any inversion caused by OPT_TXINV.
Enables the automatic update of RTC_P and RTC_Q every time the temperature
is measured.
The de-bounced state of the PB pin.
The IC sets these bits to indicate that a parity error on the remote sensor has
been detected. Once set, the bits are remembered until they are cleared by
the MPU.
Indicates that the clock generation PLL is settled.
OPT_FDC
00
01
10
11
00 = DIO51, 01 = OPT_TX, 10 = WPULSE, 11 = VARPULSE
xx = SEG51
Function
50% Low
25% Low
12.5% Low
6.25% Low
page
under the “Bit Banged Optical UART
71M6541D/F/G and 71M6542F/G Data Sheet
58.
119