DS28E02 Maxim, DS28E02 Datasheet - Page 6

• Manufacturer Part Number: DS28E02
• Description: The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm (SHA-1)
• Manufacturer: Maxim

1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
27: Understanding and Using Cyclic Redundancy
Checks with Maxim iButton Products .
The shift register bits are initialized to 0. Then, starting
with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, the serial number is entered. After
the 48th bit of the serial number has been entered, the
shift register contains the CRC value. Shifting in the 8
bits of the CRC returns the shift register to all 0s.
Figure 2. Hierarchic Structure for 1-Wire Protocol
Figure 3. 64-Bit ROM
Figure 4. 1-Wire CRC Generator
6
_______________________________________________________________________________________
1-Wire ROM FUNCTION COMMANDS
X
0
DEVICE-SPECIFIC MEMORY
FUNCTION COMMANDS
MSB
MSB
STAGE
COMMAND LEVEL:
1ST
(SEE FIGURE 10)
(SEE FIGURE 8)
CRC CODE
X
1
8-BIT
STAGE
2ND
LSB
ABRIDGED DATA SHEET
X
2
MSB
STAGE
3RD
AVAILABLE COMMANDS:
READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
OVERDRIVE-SKIP ROM
OVERDRIVE-MATCH ROM
Refer to the full data sheet.
X
3
STAGE
4TH
POLYNOMIAL = X
48-BIT SERIAL NUMBER
DS28E02
X
4
8
+ X
5
STAGE
The DS28E02 has four memory areas: data memory,
secrets memory, register page with special function
registers and user bytes, and a volatile scratchpad. The
data memory is organized as four pages of 32 bytes.
DATA FIELD AFFECTED:
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
RC-FLAG
RC-FLAG
RC-FLAG, OD-FLAG
64-BIT REG.#, RC-FLAG, OD-FLAG
5TH
+ X
4
+ 1
X
5
STAGE
6TH
LSB
X
6
MSB
STAGE
Memory Access
7TH
8-BIT FAMILY CODE
X
INPUT DATA
7
STAGE
8TH
LSB
LSB
X
8