DS28E02 Maxim, DS28E02 Datasheet - Page 5

• Manufacturer Part Number: DS28E02
• Description: The DS28E02 combines 1024 bits of EEPROM with challenge-and-response authentication security implemented with the FIPS 180-3 Secure Hash Algorithm (SHA-1)
• Manufacturer: Maxim

or consumable authentication and calibration, and
printer cartridge configuration and monitoring.
The block diagram in Figure 1 shows the relationships
between the major control and memory sections of the
DS28E02. The DS28E02 has six main data compo-
nents: 64-bit ROM, 64-bit scratchpad, four 256-bit
pages of EEPROM, register page, and a 512-bit SHA-1
engine. Figure 2 shows the hierarchic structure of the
1-Wire protocol. The bus master must first provide one
of the seven ROM function commands: Read ROM,
Match ROM, Search ROM, Skip ROM, Resume
Communication, Overdrive-Skip ROM, or Overdrive-
Match ROM. Upon completion of an Overdrive-Skip
ROM or Overdrive-Match ROM command executed at
standard speed, the device enters overdrive mode
where all subsequent communication occurs at a higher
Figure 1. Block Diagram
_______________________________________________________________________________________
ABRIDGED DATA SHEET
DS28E02
1-Wire NET
1-Wire SHA-1 Authenticated 1Kb
Overview
1-Wire FUNCTION
SHA-1 FUNCTION
DATA MEMORY
CONTROL UNIT
256 BITS EACH
MEMORY AND
EEPROM with 1.8V Operation
GENERATOR
4 PAGES OF
CONTROL
REGISTER
CRC16
PAGE
PARASITE POWER
speed. The protocol required for these ROM function
commands is described in Figure 10. After a ROM
function command is successfully executed, the mem-
ory and SHA-1 functions become accessible and the
master can provide any one of the 9 available function
commands. The function protocols are described in
Figure 8. All data is read and written least signifi-
cant bit first.
Each DS28E02 contains a unique ROM registration num-
ber that is 64 bits long. The first 8 bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The
last 8 bits are a cyclic redundancy check (CRC) of the
first 56 bits. See Figure 3 for details. The 1-Wire CRC is
generated using a polynomial generator consisting of a
shift register and XOR gates as shown in Figure 4. The
polynomial is X
about the 1-Wire CRC is available in Application Note
ALGORITHM ENGINE
SECURE HASH
SCRATCHPAD
8
512-BIT
64-BIT
64-BIT
ROM
+ X
5
+ X
4
+ 1. Additional information
64-Bit ROM
5