STR750FV2 STMicroelectronics, STR750FV2 Datasheet - Page 58

• Manufacturer Part Number: STR750FV2
• Description: ARM7TDMI-S™ 32-BIT MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN
• Manufacturer: STMicroelectronics

Specifications of STR750FV2

• Smart Low Power Modes: SLOW, WFI, STOP and STANDBY with backup registers
• Conversion Time: min. 3.75 μs

Electrical parameters
58/84
NRSTIN and NRSTOUT pins
NRSTIN Pin Input Driver is TTL/LVTTL as for all GP I/Os. A permanent pull-up is present
which is the same as R
NRSTOUT Pin Output Driver is equivalent to the O2 type driver except that it works only as
an open-drain (the P-MOS is de-activated). A permanent pull-up is present which is the
same as R
Subject to general operating conditions for V
Table 35. NRSTIN and NRSTOUT pins
1. Data based on product characterisation, not tested in production.
2. Hysteresis voltage between Schmitt trigger switching levels.
3. The I
4. The R
5. To guarantee the reset of the device, a minimum pulse of 15 µs has to be applied to the internal reset. At
6. The reset network (the resistor and two capacitors) protects the device against parasitic resets, especially
7. In fact the filter is made to ignore all incoming pulses with short duration:
V
R
V
V
V
t
hys(NRSTIN)
OL(NRSTIN)
w(RSTL)out
t
t
PU(NRSTIN)
sum of I
V
is established, an external reset pulse will be internally stretched up to 15 µs thanks to the reset pulse
stretcher.
in noisy environments.
- all negative spikes with a duration less than 150 ns are filtered
- all trains of negative spikes with a ratio of 1/2 are filtered. This means that all spikes with a maximum
duration of 150 ns with minimum interval between spikes of 75 ns are filtered.
Data guaranteed by design, not tested in production.
Symbol
IH(NRSTIN)
IL(NRSTIN)
h(RSTL)in
g(RSTL)in
DD_IO
IO
PU
power-up, the built-in reset stretcher may not generate the 15 µs pulse duration while once V
current sunk must always respect the absolute maximum rating specified in
IO
pull-up equivalent resistor are based on a resistive transistor
PU
(I/O ports and control pins) must not exceed I
(see
NRSTIN Input low level
voltage
NRSTIN Input high level
voltage
NRSTIN Schmitt trigger
voltage hysteresis
NRSTOUT Output low level
voltage
NRSTIN Weak pull-up
equivalent resistor
Generated reset pulse
duration (visible at NRSTOUT
pin)
External reset pulse hold time
at NRSTIN pin
maximum negative spike
duration filtered at NRSTIN
pin
(7)
(5)
: General characteristics on page
(1)
(1)
(3)
PU
Parameter
(see
(6)
(2)
(4)
: General characteristics on page
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
I
V
Internal reset source
At V
When V
established
The time between two
spikes must be higher
than 1/2 of the spike
duration.
IO
DD_IO
IN
=+2 mA
=
DD_IO
V
VSS
SS
Conditions
and T
DD_IO
.
54)
power-up
V
V
(5)
DD_IO
DD_IO
A
is
unless otherwise specified.
=3.3 V
=5 V
(5)
54)
Min Typ
25
20
15
20
2
1
Section 6.2.2
400
150
50
31
20
1)
Max Unit
100
100
0.8
0.4
and the
DD_IO
mV
kΩ
kΩ
μs
μs
μs
ns
V
V