STR750FV2 STMicroelectronics, STR750FV2 Datasheet - Page 21

• Manufacturer Part Number: STR750FV2
• Description: ARM7TDMI-S™ 32-BIT MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN
• Manufacturer: STMicroelectronics

Specifications of STR750FV2

• Smart Low Power Modes: SLOW, WFI, STOP and STANDBY with backup registers
• Conversion Time: min. 3.75 μs

STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Table 6.
1. For STR755FVx part numbers, the USB pins must be left unconnected.
2. The non available pins on LQPFP64 and LFBGA64 packages are internally tied to low level.
3. None of the I/Os are True Open Drain: when configured as Open Drain, there is always a protection diode between the I/O
4. In the 100-pin package, this Alternate Function is duplicated on two ports. You can configure one port to use this AF, the
5. It is mandatory that the NJTRST pin is reset to ground during the power-up phase. It is recommended to connect this pin to
6. After reset, these pins are enabled as JTAG alternate function see
7. There are two different TQFP and BGA 64-pin packages: in the first one, pins 41 and 42 are mapped to USB DN/DP while
8. For details on remapping these alternate functions, refer to the GPIO_REMAP0R register description.
100
91
92
93
94
95
96
97
98
99
pin and VDD_IO.
other port is then free for general purpose I/O (GPIO), external interrupt/wake-up lines, or analog input (ADC_IN) where
these functions are listed in the table.
NRSTOUT pin (if available) or NRSTIN.
general purpose I/O (GPIO), the DBGOFF control bit in the GPIO_REMAP0R register must be set by software (in this case,
debugging these I/Os via JTAG is not possible).
for the second one, they are mapped to P0.15/CAN_TX and P0.14/CAN_RX.
Pin n°
D5
C4
D4
D3
C3
A4
A3
A2
E6
A1
59 A3
60 C4 V18
61 C5 VSS18
62 A2 VSS_IO
63 B2 VDD_IO
64 A1
STR750F pin description (continued)
P1.04 / PWM3N /
ADC_IN9
P1.14 /
ADC_IN15
P1.13 /
ADC_IN14
P1.01 / TIM0_TI2
P1.00 /
TIM0_OC2
P0.03 / TIM2_TI1
/ ADC_IN1
Pin name
I/O
I/O
I/O
I/O
I/O
I/O
S
S
S
S
T
T
T
T
T
T
T
T
T
T
T
T
X
X
X
X
X
X
Input
X
X
X
X
X
X
EIT13
O4
O8
O8
O2
O2
O2
Output
OD
(3)
(Port reset state on page
X
X
X
X
X
X
PP
X
X
X
X
X
X
Port 1.04
Port 1.14
Port 1.13
Port 1.01
Port 1.00
Stabilization for main voltage regulator. Requires
external capacitors 33nF between V18 and VSS18.
See
To be connected to the 1.8V external power supply
when embedded regulators are not used.
Ground Voltage for the main voltage regulator.
Ground Voltage for digital I/Os
Supply Voltage for digital I/Os
Port 0.03
function
reset)
(after
Main
Figure
4.2.
16). To use these ports as
PWM: PWM3
complementary
output
ADC: analog input 15
ADC: analog input 14
TIM0: Input Capture / trigger /
external clock 2 (remappable to
P0.05)
TIM0: Output compare 2
(remappable to P0.04)
TIM2: Input
Capture / trigger
/ external clock 1
Alternate function
(4)
(8)
Pin description
ADC: analog
input 9
ADC: analog
input 1
(8)
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