STR750FV2 STMicroelectronics, STR750FV2 Datasheet - Page 16

• Manufacturer Part Number: STR750FV2
• Description: ARM7TDMI-S™ 32-BIT MCU with Flash, SMI, 3 std 16-bit timers, PWM timer, fast 10-bit ADC, I2C, UART, SSP, USB and CAN
• Manufacturer: STMicroelectronics

Specifications of STR750FV2

• Smart Low Power Modes: SLOW, WFI, STOP and STANDBY with backup registers
• Conversion Time: min. 3.75 μs

Pin description
Table 6.
16/84
1
2
3
4
5
6
Pin n°
C2
C1
D2
B1
B2
B3
1
2
3
4
B1
C2
C1
C3
Port reset state
The reset state of the I/O ports is GPIO input floating. Exceptions are P1[19:16] and P0.13
which are configured as JTAG alternate functions:
●
●
●
●
●
●
To avoid excess power consumption, unused I/O ports must be tied to ground.
STR750F pin description
P1.12 /
ADC_IN13
P0.02 /
TIM2_OC1 /
ADC_IN0
P0.01 / TIM0_TI1
/ MCO
P0.00 /
TIM0_OC1 /
BOOT0
P0.31 / TIM1_TI2
P0.30 /
TIM1_OC2
The JTAG inputs (JTDI, JTMS and JTDI) are configured as input floating and are ready
to accept JTAG sequences.
The JTAG output JTDO is configured as floating when idle (no JTAG operation) and is
configured in output push-pull only when serial JTAG data must be output.
The JTAG output RTCK is always configured as output push-pull. It outputs '0' level
during the reset phase and then outputs the JTCK input signal resynchronized 3 times
by the internal AHB clock.
The GPIO_PCx registers do not control JTAG AF selection, so the reset values of
GPIO_PCx for P1[19:16] and P0. 13 are the same as other ports. Refer to the GPIO
section of the STR750 Reference Manual for the register description and reset values.
P0.11 and P0.00 are sampled by the boot logic after reset, prior to fetching the first
word of user code at address 0000 0000h.
When booting from SMI (and only in this case), the reset state of the following GPIOs is
"SMI alternate function output enabled":
–
–
–
–
Note that the other SMI pins: SMI_CS1,2,3 (P0.12, P0.11, P0.10) are not affected.
Pin name
P0.07 (SMI_DOUT)
P0.05 (SMI_CLK)
P0.04 (SMI_CS0)
P0.06 (SMI_DIN)
I/O
I/O
I/O
I/O
I/O
I/O
T
T
T
T
T
T
T
T
T
T
T
T
X
X
X
X
X
X
Input
X
X
X
X
X
X
EIT12
EIT0
O8
O8
O8
O8
O2
O2
STR750Fxx STR751Fxx STR752Fxx STR755Fxx
Output
OD
(3)
X
X
X
X
X
X
PP
X
X
X
X
X
X
Port 1.12
Port 0.02
Port 0.01
Port 0.00 /
Boot mode
selection
input 0
Port 0.31
Port 0.30
function
reset)
(after
Main
ADC: Analog
input 13
TIM2: Output
Compare 1
TIM0: Input
Capture / trigger
/ external clock 1
TIM0: Output Compare 1
TIM1: Input Capture / trigger /
external clock 2
TIM1: Output Compare 2
Alternate function
(4)
ADC: Analog
input 0
Main Clock
Output