ST92124V1Q-Auto STMicroelectronics, ST92124V1Q-Auto Datasheet - Page 418

• Manufacturer Part Number: ST92124V1Q-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST92124V1Q-Auto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
KNOWN LIMITATIONS (Cont’d)
T
Figure 170. Critical Window Timing Diagram
Figure 171. Reception of a Sequence of Frames
Side-effect of Workround 1
Because the while loop lasts 16 CPU cycles, if
f
a dominant state on the bus if it lasts just one CAN
bit time and the bus speed is high enough (see
Table
Table 76. While Loop Timing
Note: As can be seen from the above table, no
side effect occurs in cases when f
higher and if the CAN baud rate is below 1MBaud.
418/430
1
CPU
CAN frame
FMP
BUS
CPU
24 MHz
16 MHz
8 MHz
4 MHz
≤ 16MHz at high baud rate, it is possible to miss
f
f
CPU
CPU
76)
: This is minimum CAN frame duration
T
CAN frame
Baud rate for possible
No dominant bit missed
missed dominant bit
0
> f
> 500 kHz
> 250 kHz
1 MBaud
1
Acknowledge: last
dominant bit in the frame
CPU
/ 16
CPU
Time to test RX pin and to
release the FIFO 4.5 µs@4MHz Time between the end of the
is 16MHz or
T
T
IT disable
CAN frame
CAN Frame
1
If this happens, we will continue waiting in the
while loop instead of releasing the FIFO immedi-
ately. The workaround is still valid because we will
not release the FIFO during the critical period. But
the application may lose additional time waiting in
the while loop as we are no longer able to guar-
antee a maximum of 6 CAN bit times spent in the
workaround.
In this particular case the time the application can
spend in the workaround may increase up to a full
CAN frame, depending of the frame contents. This
case is very rare but happens when a specific se-
quence is present on in the CAN frame.
The example in
TCAN is 12/f
If the application is using the maximum baud rate
and the possible delay caused by the workaround
is not acceptable, there is another workaround
which reduces the Rx pin sampling time.
2
T
IT higher level
acknowledge and the critical windows
- 6 full CAN bit times+ time to the sample point
approx. 13µs @ 500kBd
Critical window: the received
message is placed in the FIFO
CPU
and the sampling time is 16/f
T
Figure 172
CAN frame
2
T
IT CAN
3
shows reception if
A release is not
allowed at this time
2
CPU
.