ST92124V1Q-Auto STMicroelectronics, ST92124V1Q-Auto Datasheet - Page 110

• Manufacturer Part Number: ST92124V1Q-Auto
• Description: 8-bit MCU for automotive
• Manufacturer: STMicroelectronics

Specifications of ST92124V1Q-Auto

• Internal Memory: Single Voltage FLASH up to 256 Kbytes, RAM up to 8Kbytes, 1K byte E3 TM (Emulated EEPROM)
• Minimum Instruction Time: 83 ns (24 MHz int. clock)

ST92124xxx-Auto/150xxxxx-Auto/250xxxx-Auto
INTERRUPT REGISTERS (Cont’d)
INTERRUPT
(SIPRL)
R250 - Read/Write
Register Page: 60
Reset value: 0000 0000 (00h)
Bits 7:0 = IPxx Channel E-H Pending bits
The IPxx bits are set by hardware on occurrence
of the trigger event. (as specified in the ITR regis-
ter) and are cleared by hardware on interrupt ac-
knowledge.
0 : No interrupt pending
1 : Interrupt pending
Note: IPR bits may be set by the user to imple-
ment a software interrupt.
STANDARD INTERRUPT VECTOR REGISTER
(SIVR)
R251 - Read/Write
Register Page: 60
Reset value: xxx1 1110 (xE)
Bits 7:5 = V[7:5] MSBs of Channnel E to L inter-
rupt vector address
These bits are not initialized by reset. For a repre-
sentation of how the full vector is generated from
V[7:5], refer to
110/430
9
IPH1
V7
7
7
IPH0
V6
IPG1
V5
Figure
PENDING
IPG0
W3
53.
IPF1
W2
REGISTER
IPF0
W1
IPE1
W0
IPE0
LOW
0
0
0
Bits 4:1 = W[3:0] Arbitration Winner Bits
These bits are set and cleared by hardware de-
pending upon the channel which emerges as a
winner as shown in the following table.
At the start of interrupt/DMA arbitration (IC0 = 0)
the W[3:0] bits are latched. They remain stable
through the entire arbitration cycle. Even if a inter-
rupt of higher priority comes after the start of int/
DMA arbitration, the SIVR register is not updated.
This new request will be taken into account in the
next arbitration cycle.
Bit 0 = Reserved, fixed by hardware to 0.
INTERRUPT
HIGH (SIPLRH)
R252 - Read/Write
Register Page: Page 60
Reset Value : 1111 1111
Bits 1:0 = PL2I, PL1I: INTI0, I1 Priority Level.
These bits are set and cleared by software.
The priority is a three-bit value. The LSB is fixed by
hardware at 0 for even channels and at 1 for odd
channels
7
Interrupt Channel pair
-
-
INTG0
INTG1
INTE0
INTE1
INTH0
INTH1
INTF0
INTF1
INTI0
PRIORITY
-
-
-
LEVEL
-
W[3:0]
1000
REGISTER
0000
0001
0010
0011
0100
0101
0110
0111
PL2I
PL1I
0