ST72321AR6-Auto STMicroelectronics, ST72321AR6-Auto Datasheet - Page 6
ST72321AR6-Auto
Manufacturer Part Number
ST72321AR6-Auto
Description
8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
Manufacturer
STMicroelectronics
Datasheet
1.ST72321R9-AUTO.pdf
(243 pages)
Specifications of ST72321AR6-Auto
Hdflash Endurance
100 cycles, data retention 20 years
Clock Sources
crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
4 Power Saving Modes
Halt, Active Halt, Wait and Slow
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Contents
14
6/243
Serial peripheral interface (SPI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.1
14.2
14.3
14.4
14.5
14.6
14.7
14.8
13.7.4
13.7.5
13.7.6
13.7.7
13.7.8
13.7.9
13.7.10 Counter high register (CHR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.7.11 Counter low register (CLR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
13.7.12 Alternate counter high register (ACHR) . . . . . . . . . . . . . . . . . . . . . . . . 118
13.7.13 Alternate counter low register (ACLR) . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.7.14 Input capture 2 high register (IC2HR) . . . . . . . . . . . . . . . . . . . . . . . . . 119
13.7.15 Input capture 2 low register (IC2LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Main features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
14.3.1
14.3.2
14.3.3
14.3.4
14.3.5
14.3.6
Clock phase and clock polarity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Error flags . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
14.5.1
14.5.2
14.5.3
14.5.4
Low power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
14.6.1
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
SPI registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
14.8.1
14.8.2
14.8.3
Input capture 1 high register (IC1HR) . . . . . . . . . . . . . . . . . . . . . . . . . 116
Input capture 1 low register (IC1LR) . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Output compare 1 high register (OC1HR) . . . . . . . . . . . . . . . . . . . . . . 117
Output compare 1 low register (OC1LR) . . . . . . . . . . . . . . . . . . . . . . . 117
Output compare 2 high register (OC2HR) . . . . . . . . . . . . . . . . . . . . . . 117
Output compare 2 low register (OC2LR) . . . . . . . . . . . . . . . . . . . . . . . 118
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Slave select management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Master mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Master mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Slave mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Slave mode transmit sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Master mode fault (MODF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Overrun condition (OVR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Write collision error (WCOL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Single master systems . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Using the SPI to wake up the MCU from Halt mode . . . . . . . . . . . . . . 130
Control register (SPICR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
Control/status register (SPICSR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Data I/O register (SPIDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Doc ID 13829 Rev 1
ST72321xx-Auto
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