ST72321AR6-Auto STMicroelectronics, ST72321AR6-Auto Datasheet - Page 116

• Manufacturer Part Number: ST72321AR6-Auto
• Description: 8-bit MCU for automotive with 32 Kbyte Flash, 10-bit ADC, timers, SPI, SCI and I2C interfaces
• Manufacturer: STMicroelectronics

Specifications of ST72321AR6-Auto

• Hdflash Endurance: 100 cycles, data retention 20 years
• Clock Sources: crystal/ceramic resonator oscillators, internal RC oscillator and bypass for external clock
• 4 Power Saving Modes: Halt, Active Halt, Wait and Slow

16-bit timer
13.7.4
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Table 62.
Input capture 1 high register (IC1HR)
This is an 8-bit read only register that contains the high part of the counter value (transferred
by the input capture 1 event).
IC1HR
Bit
1:0
7
6
5
4
3
2
MSB
RO
7
Name
OCF1
OCF2
TIMD
ICF1
ICF2
TOF
-
CSR register description
Input Capture Flag 1
Output Compare Flag 1
Timer Overflow Flag
Output Compare Flag 2
Timer disable
Reserved, must be kept cleared
RO
Input Capture Flag 2
6
0: No input capture (reset value)
1: An input capture has occurred on the ICAP1 pin or the counter has reached the
OC2R value in PWM mode. To clear this bit, first read the SR register, then read
or write the low byte of the IC1R (IC1LR) register.
0: No match (reset value)
1: The content of the free running counter has matched the content of the OC1R
register. To clear this bit, first read the SR register, then read or write the low byte
of the OC1R (OC1LR) register.
0: No timer overflow (reset value)
1: The free running counter rolled over from FFFFh to 0000h. To clear this bit, first
read the SR register, then read or write the low byte of the CR (CLR) register.
Note: Reading or writing the ACLR register does not clear TOF.
0: No input capture (reset value).
1: An input capture has occurred on the ICAP2 pin. To clear this bit, first read the
SR register, then read or write the low byte of the IC2R (IC2LR) register.
0: No match (reset value)
1: The content of the free running counter has matched the content of the OC2R
register. To clear this bit, first read the SR register, then read or write the low byte
of the OC2R (OC2LR) register.
This bit is set and cleared by software. When set, it freezes the timer prescaler
and counter and disabled the output functions (OCMP1 and OCMP2 pins) to
reduce power consumption. Access to the timer registers is still available, allowing
the timer configuration to be changed, or the counter reset, while it is disabled.
0: Timer enabled
1: Timer prescaler, counter and outputs disabled
RO
5
Doc ID 13829 Rev 1
RO
4
Function
RO
3
RO
2
Reset value: Undefined
RO
1
ST72321xx-Auto
LSB
RO
0